Processor with 4.9-μs break-even time in power gating using crystalline In-Ga-Zn-oxide transistor. - Hidetomo Kobayashi; Kiyoshi Kato; Takuro Ohmaru; Seiichi Yoneda; Tatsuji Nishijima; Shuhei Maeda; Kazuaki Ohshima; Hikaru Tamura; Hiroyuki Tomatsu; Tomoaki Atsumi; Yutaka Shionoiri; Yukio Maehashi; et al. (COOL Chips, 2013)

Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating. - Hikaru Tamura; Kiyoshi Kato; Takahiko Ishizu; Tatsuya Onuki; Wataru Uesugi; Takuro Ohmaru; Kazuaki Ohshima; Hidetomo Kobayashi; Seiichi Yoneda; Atsuo Isobe; Naoaki Tsutsui; Suguru Hondo; et al. (COOL Chips, 2014)

A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor. - Atsuo Isobe; Hikaru Tamura; Kiyoshi Kato; Takuro Ohmaru; Wataru Uesugi; Takahiko Ishizu; Tatsuya Onuki; Kazuaki Ohshima; Takanori Matsuzaki; Atsushi Hirose; Yasutaka Suzuki; Naoaki Tsutsui; et al. (VLSIC, 2014)

Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor. - Hikaru Tamura; Kiyoshi Kato; Takahiko Ishizu; Wataru Uesugi; Atsuo Isobe; Naoaki Tsutsui; Yasutaka Suzuki; Yutaka Okazaki; Yukio Maehashi; Jun Koyama; Yoshitaka Yamamoto; Shunpei Yamazaki; et al. (IEEE Micro, 2014)

Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS. - Tatsuya Onuki; Wataru Uesugi; Hikaru Tamura; Atsuo Isobe; Yoshinori Ando; Satoru Okamoto; Kiyoshi Kato; Tri Rung Yew; Chen Bin Lin; J. Y. Wu; Chi Chang Shuai; Shao Hui Wu; et al. (VLSI Circuits, 2016)