Modeling design constraints and biasing in simulation using BDDs. - Jun Yuan 007; Kurt Shultz; Carl Pixley; Hillel Miller; Adnan Aziz (ICCAD, 1999)

Saving Space by Fully Exploiting Invisible Transitions. - Shmuel Katz; Hillel Miller (Formal Methods Syst. Des., 1999)

Automatic Vector Generation Using Constraints and Biasing. - Jun Yuan 007; Kurt Shultz; Carl Pixley; Hillel Miller; Adnan Aziz (J. Electron. Test., 2000)

Evaluating and comparing simulation verification vs. formal verification approach on block level design. - Eyal Segev; Sharon Goldshlager; Hillel Miller; Oren Shua; Olga Sher; Shlomo Greenberg (ICECS, 2004)

SOC modeling methodology for architectural exploration and software development. - Michal Silbermintz; Amir Sahar; Itay Peled; Moshe Anschel; Emil Watralov; Hillel Miller; Eytan Weisberger (ICECS, 2004)

Reusable On-Chip System Level Verification for Simulation Emulation and Silicon. - Avishay Maman; Sharon Goldschlager; Hillel Miller; David Bell; Rob Slater; Oded Ben-Moshe; Nissan Levi; Hagit Gilboa (HLDVT, 2006)

Extracting a Simplified View of Design Functionality Based on Vector Simulation. - Onur Guzey; Charles H.-P. Wen; Li-C. Wang; Tao Feng 012; Hillel Miller; Magdy S. Abadir (Haifa Verification Conference, 2006)

An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs. - Mrinal Bose; Prashant Naphade; Jayanta Bhadra; Hillel Miller (ISQED, 2009)