Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse. - Daniel A. Connors; Hillery C. Hunter; Ben-Chung Cheng; Wen-mei W. Hwu (ASPLOS, 2000)

Enhancing loop buffering of media and telecommunications applications using low-overhead predication. - John W. Sias; Hillery C. Hunter; Wen-mei W. Hwu (MICRO, 2001)

Code coverage and input variability: effects on architecture and compiler research. - Hillery C. Hunter; Wen-mei W. Hwu (CASES, 2002)

A new look at exploiting data parallelism in embedded systems. - Hillery C. Hunter; Jaime H. Moreno (CASES, 2003)

An innovative low-power high-performance programmable signal processor for digital communications. - Jaime H. Moreno; Victor V. Zyuban; Uzi Shvadron; Fredy D. Neeser; Jeff H. Derby; Malcolm S. Ware; Krishnan Kailas; Ayal Zaks; Amir B. Geva; Shay Ben-David; Sameh W. Asaad; Thomas W. Fox; et al. (IBM J. Res. Dev., 2003)

Matching on -Chip Data Storage to Telecommunication and Media Application Properties - Hillery C. Hunter (2004)

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. - John Barth 001; William R. Reohr; Paul C. Parries; Gregory Fredeman; John Golz; Stanley Schuster; Richard E. Matick; Hillery C. Hunter; Charles Tanner; Joseph Harig; Hoki Kim; Babar A. Khan; et al. (ISSCC, 2007)

Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve? - Hillery C. Hunter (ISQED, 2008)

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. - John Barth 001; William R. Reohr; Paul C. Parries; Gregory Fredeman; John Golz; Stanley Schuster; Richard E. Matick; Hillery C. Hunter; Charles Tanner; Joseph Harig; Hoki Kim; Babar A. Khan; et al. (IEEE J. Solid State Circuits, 2008)

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. - Peter J. Klim; John Barth 001; William R. Reohr; David Dick; Gregory Fredeman; Gary Koch; Hien M. Le; Aditya Khargonekar; Pamela Wilcox; John Golz; Jente B. Kuang; Abraham Mathews; et al. (IEEE J. Solid State Circuits, 2009)

Hardware-compiler co-design for adjustable data power savings. - Hillery C. Hunter; Erik M. Nystrom; Daniel A. Connors; Wen-mei W. Hwu (Microprocess. Microsystems, 2009)

The virtual write queue: coordinating DRAM and last-level cache policies. - Jeffrey Stuecheli; Dimitris Kaseridis; David Daly; Hillery C. Hunter; Lizy K. John (ISCA, 2010)

Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory. - Jeffrey Stuecheli; Dimitris Kaseridis; Hillery C. Hunter; Lizy K. John (MICRO, 2010)

Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue. - Jeffrey Stuecheli; Dimitris Kaseridis; David Daly; Hillery C. Hunter; Lizy K. John (IEEE Micro, 2011)

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. - Janani Mukundan; Hillery C. Hunter; Kyu-Hyoun Kim; Jeffrey Stuecheli; José F. Martínez (ISCA, 2013)

Adapting Server Systems for New Memory Technologies. - Hillery C. Hunter; Luis Alfonso Lastras-Montaño; Bishwaranjan Bhattacharjee (Computer, 2014)

Guest Editorial Computing in Emerging Technologies (First Issue). - Saibal Mukhopadhyay; Swarup Bhunia; Hillery C. Hunter; Kaushik Roy 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Guest Editorial Computing in Emerging Technologies (Second Issue). - Saibal Mukhopadhyay; Swarup Bhunia; Hillery C. Hunter; Kaushik Roy 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

PANEL: Open panel and discussion on tackling complexity, reproducibility and tech transfer challenges in a rapidly evolving AI/ML/systems research. - Grigori Fursin; Thierry Moreau; Hillery C. Hunter; Yiran Chen 001; Charles Qi; Tianqi Chen 001 (ReQuEST@ASPLOS, 2018)

BlueConnect: Decomposing All-Reduce for Deep Learning on Heterogeneous Network Hierarchy. - Minsik Cho; Ulrich Finkler; David S. Kung 001; Hillery C. Hunter (SysML, 2019)

BlueConnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy. - Minsik Cho; Ulrich Finkler; Mauricio J. Serrano; David S. Kung 001; Hillery C. Hunter (IBM J. Res. Dev., 2019)

Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem. - Saravanan Sethuraman; Venkata Kalyan Tavva; Karthick Rajamani; Chitra K. Subramanian; Kyu-Hyoun Kim; Hillery C. Hunter; M. B. Srinivas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)