Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs - Abhishek Jain 003; Giuseppe Bonanno; Hima Gupta; Ajay Goyal (CoRR, 2013)

Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator. - Abhishek Jain 003; Piyush Kumar Gupta; Hima Gupta; Sachish Dhar (CoRR, 2014)

Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL. - Abhishek Jain 003; Hima Gupta; Sandeep Jana; Krishna Kumar (CoRR, 2014)