Future Performance Challenges in Nanometer Design. - Dennis Sylvester; Himanshu Kaul (DAC, 2001)

Power-Driven Challenges in Nanometer Design. - Dennis Sylvester; Himanshu Kaul (IEEE Des. Test Comput., 2001)

Active shields: a new approach to shielding global wires. - Himanshu Kaul; Dennis Sylvester; David T. Blaauw (ACM Great Lakes Symposium on VLSI, 2002)

Transition Aware Global Signaling (TAGS). - Himanshu Kaul; Dennis Sylvester (ISQED, 2002)

Active shielding of RLC global interconnects. - Himanshu Kaul; Dennis Sylvester; David T. Blaauw (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

Clock net optimization using active shielding. - Himanshu Kaul; Dennis Sylvester; David T. Blaauw (ESSCIRC, 2003)

Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. - Himanshu Kaul; Dennis Sylvester; Mark A. Anders 001; Ram Krishnamurthy 001 (ISLPED, 2004)

Performance optimization of critical nets through active shielding. - Himanshu Kaul; Dennis Sylvester; David T. Blaauw (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Low-power on-chip communication based on transition-aware global signaling (TAGS). - Himanshu Kaul; Dennis Sylvester (IEEE Trans. Very Large Scale Integr. Syst., 2004)

DVS for On-Chip Bus Designs Based on Timing Error Correction. - Himanshu Kaul; Dennis Sylvester; David T. Blaauw; Trevor N. Mudge; Todd M. Austin (DATE, 2005)

A 2GHz 13.6mW 12 × 9b multiplier for energy efficient FFT accelerators. - Steven Hsu; Vishak Venkatraman; Sanu Mathew; Himanshu Kaul; Mark A. Anders 001; Saurabh Dighe; Wayne P. Burleson; Ram Krishnamurthy 001 (ESSCIRC, 2005)

A novel buffer circuit for energy efficient signaling in dual-VDD systems. - Himanshu Kaul; Dennis Sylvester (ACM Great Lakes Symposium on VLSI, 2005)

Power-aware global signaling strategies. - Rahul M. Rao; Kanak Agarwal 001; Dennis Sylvester; Himanshu Kaul; Richard B. Brown; Sani R. Nassif (ISCAS (1), 2005)

High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS. - Himanshu Kaul (SoCC, 2005)

Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. - Himanshu Kaul; Dennis Sylvester; Mark A. Anders 001; Ram Krishnamurthy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects. - Vishak Venkatraman; Mark A. Anders 001; Himanshu Kaul; Wayne P. Burleson; Ram Krishnamurthy 001 (SoCC, 2006)

A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS. - Mark A. Anders 001; Himanshu Kaul; Martin Hansson; Ram Krishnamurthy 001; Shekhar Borkar (ESSCIRC, 2008)

A robust alternate repeater technique for high performance busses in the multi-core era. - Himanshu Kaul; Jae-sun Seo; Mark A. Anders 001; Dennis Sylvester; Ram Krishnamurthy 001 (ISCAS, 2008)

A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu Mathew; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2008)

A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu Mathew; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2009)

A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu K. Mathew; Steven Hsu; Amit Agarwal 001; Ram K. Krishnamurthy; Shekhar Borkar (IEEE J. Solid State Circuits, 2009)

3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS. - Sanu Mathew; Michael E. Kounavis; Farhana Sheikh; Steven Hsu; Amit Agarwal 001; Himanshu Kaul; Mark A. Anders 001; Frank L. Berry; Ram Krishnamurthy 001 (ESSCIRC, 2010)

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS. - Rajaraman Ramanarayanan; Sanu Mathew; Farhana Sheikh; Suresh Srinivasan; Amit Agarwal 001; Steven Hsu; Himanshu Kaul; Mark A. Anders 001; Vasantha Erraguntla; Ram Krishnamurthy 001 (ESSCIRC, 2010)

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. - Amit Agarwal 001; Sanu Mathew; Steven Hsu; Mark A. Anders 001; Himanshu Kaul; Farhana Sheikh; Rajaraman Ramanarayanan; Suresh Srinivasan; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2010)

A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. - Mark A. Anders 001; Himanshu Kaul; Steven Hsu; Amit Agarwal 001; Sanu Mathew; Farhana Sheikh; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2010)

A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu Mathew; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Shekhar Borkar (IEEE J. Solid State Circuits, 2010)

Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections. - Mark A. Anders 001; Himanshu Kaul; Ram K. Krishnamurthy; Shekhar Y. Borkar (Low Power Networks-on-Chip, 2011)

A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS. - Amit Agarwal 001; Steven Hsu; Sanu Mathew; Mark A. Anders 001; Himanshu Kaul; Farhana Sheikh; Ram Krishnamurthy 001 (ESSCIRC, 2011)

53 Gbps Native GF(2 4) 2 Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors. - Sanu Mathew; Farhana Sheikh; Michael E. Kounavis; Shay Gueron; Amit Agarwal 001; Steven Hsu; Himanshu Kaul; Mark A. Anders 001; Ram Krishnamurthy 001 (IEEE J. Solid State Circuits, 2011)

A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect. - Jae-sun Seo; Himanshu Kaul; Ram Krishnamurthy 001; Dennis Sylvester; David T. Blaauw (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Near-threshold voltage (NTV) design: opportunities and challenges. - Himanshu Kaul; Mark A. Anders 001; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Shekhar Borkar (DAC, 2012)

A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS. - Amit Agarwal 001; Steven Hsu; Sanu Mathew; Mark A. Anders 001; Himanshu Kaul; Farhana Sheikh; Ram Krishnamurthy 001 (ESSCIRC, 2012)

A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS. - Steven Hsu; Amit Agarwal 001; Mark A. Anders 001; Sanu Mathew; Himanshu Kaul; Farhana Sheikh; Ram Krishnamurthy 001 (ISSCC, 2012)

A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu Mathew; Steven Hsu; Amit Agarwal 001; Farhana Sheikh; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2012)

A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. - Farhana Sheikh; Sanu Mathew; Mark A. Anders 001; Himanshu Kaul; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2012)

A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. - Steven Hsu; Amit Agarwal 001; Mark A. Anders 001; Himanshu Kaul; Sanu Mathew; Farhana Sheikh; Ram Krishnamurthy 001; Shekhar Borkar (VLSIC, 2012)

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors. - Sanu Mathew; Suresh Srinivasan; Mark A. Anders 001; Himanshu Kaul; Steven Hsu; Farhana Sheikh; Amit Agarwal 001; Sudhir Satpathy; Ram Krishnamurthy 001 (IEEE J. Solid State Circuits, 2012)

A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS. - Steven Hsu; Amit Agarwal 001; Mark A. Anders 001; Sanu Mathew; Himanshu Kaul; Farhana Sheikh; Ram K. Krishnamurthy (IEEE J. Solid State Circuits, 2013)

A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. - Farhana Sheikh; Sanu Mathew; Mark A. Anders 001; Himanshu Kaul; Steven Hsu; Amit Agarwal 001; Ram K. Krishnamurthy; Shekhar Borkar (IEEE J. Solid State Circuits, 2013)

13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS. - Sudhir Satpathy; Sanu Mathew; Jiangtao Li 001; Patrick Koeberl; Mark A. Anders 001; Himanshu Kaul; Gregory K. Chen; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (ESSCIRC, 2014)

16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. - Gregory K. Chen; Mark A. Anders 001; Himanshu Kaul; Sudhir Satpathy; Sanu K. Mathew; Steven K. Hsu; Amit Agarwal 001; Ram K. Krishnamurthy; Shekhar Borkar; Vivek De (ISSCC, 2014)

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS. - Sanu K. Mathew; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Steven K. Hsu; Amit Agarwal 001; Gregory K. Chen; Rachael J. Parker; Ram K. Krishnamurthy; Vivek De (ISSCC, 2014)

340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Himanshu Kaul; Mark A. Anders 001; Gregory K. Chen; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (VLSIC, 2014)

μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS. - Sanu Mathew; David Johnston; Paul Newman 002; Sudhir Satpathy; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Gregory K. Chen; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (ESSCIRC, 2015)

Investigating biocomplexity through the agent-based paradigm. - Himanshu Kaul; Yiannis Ventikos (Briefings Bioinform., 2015)

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. - Gregory K. Chen; Mark A. Anders 001; Himanshu Kaul; Sudhir Satpathy; Sanu K. Mathew; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2015)

340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001 (IEEE J. Solid State Circuits, 2015)

A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Mark A. Anders 001; Gregory K. Chen; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Vivek De (A-SSCC, 2016)

14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu K. Mathew; Gregory K. Chen; Sudhir Satpathy; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001 (ISSCC, 2016)

A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS. - Amit Agarwal 001; Steven Hsu; Mark A. Anders 001; Sanu Mathew; Gregory K. Chen; Himanshu Kaul; Sudhir Satpathy; Ram Krishnamurthy 001 (VLSI Circuits, 2016)

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001; Vivek De (VLSI Circuits, 2016)

250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001 (VLSI Circuits, 2016)

µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS. - Sanu K. Mathew; David Johnston; Sudhir Satpathy; Vikram B. Suresh; Paul Newman 002; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram K. Krishnamurthy (IEEE J. Solid State Circuits, 2016)

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS. - Sudhir Satpathy; Sanu K. Mathew; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram K. Krishnamurthy; Vivek K. De (IEEE J. Solid State Circuits, 2017)

Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu Mathew; Vikram B. Suresh; Sudhir Satpathy; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (A-SSCC, 2018)

A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Vinodh Gopal; James Guilford; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (A-SSCC, 2018)

34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Vinodh Gopal; James Guilford; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Kam Krisnnamurthy (ESSCIRC, 2018)

A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. - Vikram B. Suresh; Sudhir Satpathy; Sanu Mathew; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (ESSCIRC, 2018)

2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS. - Mark A. Anders 001; Himanshu Kaul; Sanu Mathew; Vikram B. Suresh; Sudhir Satpathy; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (VLSI Circuits, 2018)

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Vivek De (VLSI Circuits, 2018)

220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(24)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS. - Sudhir Satpathy; Vikram B. Suresh; Sanu Mathew; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (VLSI Circuits, 2018)

MetaXplorer: an intelligent and adaptable metasearch engine using a novel ordered weighted averaging operator. - Neha Dimri; Himanshu Kaul; Daya Gupta (Int. J. Syst. Assur. Eng. Manag., 2018)

Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators. - Himanshu Kaul; Mark A. Anders 001; Sanu Mathew; Seongjong Kim; Ram Krishnamurthy 001 (ARITH, 2019)

A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. - Amit Agarwal 001; Steven Hsu; Monodeep Kar; Mark A. Anders 001; Himanshu Kaul; Raghavan Kumar; Vikram B. Suresh; Sanu Mathew; Ram Krishnamurthy 001; Vivek De (A-SSCC, 2019)

A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS. - Sudhir Satpathy; Vikram B. Suresh; Raghavan Kumar; Vinodh Gopal; James Guilford; Kirk Yap; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Sanu Mathew (CICC, 2019)

A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS. - Vikram B. Suresh; Sudhir Satpathy; Raghavan Kumar; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Sanu Mathew (CICC, 2019)

A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. - Steven Hsu; Amit Agarwal 001; Monodeep Kar; Mark A. Anders 001; Himanshu Kaul; Raghavan Kumar; Sudhir Satpathy; Vikram B. Suresh; Sanu Mathew; Ram Krishnamurthy 001; Vivek De (VLSI Circuits, 2019)

A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. - Raghavan Kumar; Vikram B. Suresh; Monodeep Kar; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001; Vivek De; Sanu Mathew (VLSI Circuits, 2019)

A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array. - Sudhir Satpathy; Vikram B. Suresh; Raghavan Kumar; Vinodh Gopal; James Guilford; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Vivek De; Sanu Mathew (VLSI Circuits, 2019)

A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. - Vikram B. Suresh; Sudhir Satpathy; Raghavan Kumar; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Vivek De; Sanu Mathew (VLSI Circuits, 2019)

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS. - Sudhir Satpathy; Sanu K. Mathew; Raghavan Kumar; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram K. Krishnamurthy; Vivek De (IEEE J. Solid State Circuits, 2019)

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. - Amit Agarwal 001; Steven Hsu; Simeon Realov; Mark A. Anders 001; Gregory K. Chen; Monodeep Kar; Raghavan Kumar; Huseyin Sumbul; Phil C. Knag; Himanshu Kaul; Sanu Mathew; Mahesh Kumashikar; et al. (ISSCC, 2020)

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. - Mark A. Anders 001; Himanshu Kaul; Seongjong Kim; Gregory K. Chen; Raghavan Kumar; Huseyin Ekin Sumbul; Phil C. Knag; Monodeep Kar; Steven K. Hsu; Amit Agarwal 001; Vikram B. Suresh; Sanu K. Mathew; et al. (ISSCC, 2020)

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. - Steven Hsu; Amit Agarwal 001; Simeon Realov; Mark A. Anders 001; Gregory K. Chen; Monodeep Kar; Raghavan Kumar; Huseyin Sumbul; Phil C. Knag; Himanshu Kaul; Vikram B. Suresh; Sanu Mathew; et al. (VLSI Circuits, 2020)

A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. - Monodeep Kar; Amit Agarwal 001; Steven Hsu; David Moloney; Gregory K. Chen; Raghavan Kumar; Huseyin Sumbul; Phil C. Knag; Mark A. Anders 001; Himanshu Kaul; Jonathan Byrne; Luca Sarti; et al. (VLSI Circuits, 2020)

A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. - Phil C. Knag; Gregory K. Chen; Huseyin Ekin Sumbul; Raghavan Kumar; Mark A. Anders 001; Himanshu Kaul; Steven K. Hsu; Amit Agarwal 001; Monodeep Kar; Seongjong Kim; Ram K. Krishnamurthy (VLSI Circuits, 2020)

A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures. - Raghavan Kumar; Xiaosen Liu; Vikram B. Suresh; Harish Krishnamurthy; Mark A. Anders 001; Himanshu Kaul; Krishnan Ravichandran; Vivek De; Sanu Mathew (VLSI Circuits, 2020)

A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS. - Raghavan Kumar; Sudhir Satpathy; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Vivek De; Sanu Mathew (VLSI Circuits, 2020)

A 0.26% BER, 1028 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection. - Vikram B. Suresh; Raghavan Kumar; Mark A. Anders 001; Himanshu Kaul; Vivek De; Sanu Mathew (VLSI Circuits, 2020)

A 4900- $ mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. - Raghavan Kumar; Vikram B. Suresh; Monodeep Kar; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram K. Krishnamurthy; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2020)

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. - Phil C. Knag; Gregory K. Chen; Huseyin Ekin Sumbul; Raghavan Kumar; Steven K. Hsu; Amit Agarwal 001; Monodeep Kar; Seongjong Kim; Mark A. Anders 001; Himanshu Kaul; Ram K. Krishnamurthy (IEEE J. Solid State Circuits, 2021)

A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. - Raghavan Kumar; Xiaosen Liu; Vikram B. Suresh; Harish K. Krishnamurthy; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Krishnan Ravichandran; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2021)

Balancing heterogeneous assembly line with multi-skilled human-robot collaboration via Adaptive cooperative co-evolutionary algorithm. - Bo Tian; Himanshu Kaul; Mukund Janardhanan (Swarm Evol. Comput., 2024)