Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. - Hiran Tennakoon; Carl Sechen (ICCAD, 2002)

Efficient and accurate gate sizing with piecewise convex delay models. - Hiran Tennakoon; Carl Sechen (DAC, 2005)

Nonconvex Gate Delay Modeling and Delay Optimization. - Hiran Tennakoon; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Power reduction via separate synthesis and physical libraries. - Mohammad Rahman; Ryan Afonso; Hiran Tennakoon; Carl Sechen (DAC, 2011)

Power reduction via near-optimal library-based cell-size selection. - Mohammad Rahman; Hiran Tennakoon; Carl Sechen (DATE, 2011)

Library-Based Cell-Size Selection Using Extended Logical Effort. - Mohammad Rahman; Hiran Tennakoon; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)