SystemC Kernel extensions for heterogeneous system modeling - a framework for multi-MoC modeling and simulation. - Hiren D. Patel; Sandeep Kumar Shukla (Kluwer, 2004)

A Functional Programming Framework of Heterogeneous Model of Computation for System Design. - Deepak Mathaikutty; Hiren D. Patel; Sandeep K. Shukla (FDL, 2004)

An Introductory Survey of Networked Embedded Systems. - Hiren D. Patel; Sumit Gupta; Sandeep K. Shukla; Rajesh Gupta 001 (The Industrial Information Technology Handbook, 2005)

SystemCXML: An Exstensible SystemC Front end Using XML. - David Berner; Jean-Pierre Talpin; Hiren D. Patel; Deepak Mathaikutty; Sandeep K. Shukla (FDL, 2005)

Modelling Environment for Heterogeneous Systems based on MoCs. - Deepak Mathaikutty; Hiren D. Patel; Sandeep K. Shukla; Axel Jantsch (FDL, 2005)

Towards Behavioural Hierarchy Extensions for SystemC. - Hiren D. Patel; Sandeep K. Shukla (FDL, 2005)

Automated Extraction of Structural Information from SystemC-based IP for Validation. - David Berner; Hiren D. Patel; Deepak Mathaikutty; Sandeep K. Shukla (MTV, 2005)

Towards a heterogeneous simulation kernel for system-level models: a SystemC kernel for synchronous data flow models. - Hiren D. Patel; Sandeep K. Shukla (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Design Issues for Networked Embedded Systems. - Hiren D. Patel; Sumit Gupta; Sandeep K. Shukla; Rajesh K. Gupta 001 (Embedded Systems Handbook, 2005)

Heterogeneous behavioral hierarchy for system level designs. - Hiren D. Patel; Sandeep K. Shukla; Reinaldo A. Bergamaschi (DATE, 2006)

A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design. - Hiren D. Patel; Sandeep K. Shukla; E. Mednick; Rishiyur S. Nikhil (MEMOCODE, 2006)

Deep vs. Shallow, Kernel vs. Language–What is Better for Heterogeneous Modeling in {SystemC}?. - Hiren D. Patel; Sandeep K. Shukla (MTV, 2006)

CARH: service-oriented architecture for validating system-level designs. - Hiren D. Patel; Deepak Mathaikutty; David Berner; Sandeep K. Shukla (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Performance modeling for early analysis of multi-core systems. - Reinaldo A. Bergamaschi; Indira Nair; Gero Dittmann; Hiren D. Patel; Geert Janssen; Nagu R. Dhanwada; Alper Buyuktosunoglu; Emrah Acar; Gi-Joon Nam; Dorothy Kucar; Pradip Bose; John A. Darringer; et al. (CODES+ISSS, 2007)

Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL. - Hiren D. Patel; Sandeep K. Shukla (DATE, 2007)

Heterogeneous Behavioral Hierarchy Extensions for SystemC. - Hiren D. Patel; Sandeep K. Shukla; Reinaldo A. Bergamaschi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

EWD: A metamodeling driven customizable multi-MoC system modeling framework. - Deepak Mathaikutty; Hiren D. Patel; Sandeep K. Shukla; Axel Jantsch (ACM Trans. Design Autom. Electr. Syst., 2007)

Ingredients for Successful System Level Automation & Design Methodology. - Hiren D. Patel (2007)

Ingredients for Successful System Level Design Methodology. - Hiren D. Patel; Sandeep Kumar Shukla (Springer, 2008)

Exploring power management in multi-core systems. - Reinaldo A. Bergamaschi; Guoling Han; Alper Buyuktosunoglu; Hiren D. Patel; Indira Nair; Gero Dittmann; Geert Janssen; Nagu R. Dhanwada; Zhigang Hu; Pradip Bose; John A. Darringer (ASP-DAC, 2008)

Predictable programming on a precision timed architecture. - Ben Lickly; Isaac Liu; Sungjun Kim; Hiren D. Patel; Stephen A. Edwards; Edward A. Lee (CASES, 2008)

An Automated Mapping of Timed Functional Specification to a Precision Timed Architecture. - Shanna-Shaye Forbes; Hiren D. Patel; Edward A. Lee; Hugo A. Andrade (DS-RT, 2008)

On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications. - Bijoy Antony Jose; Sandeep K. Shukla; Hiren D. Patel; Jean-Pierre Talpin (MEMOCODE, 2008)

SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system. - Deepak Mathaikutty; Hiren D. Patel; Sandeep K. Shukla; Axel Jantsch (Des. Autom. Embed. Syst., 2008)

Model-Driven Validation of SystemC Designs. - Hiren D. Patel; Sandeep K. Shukla (EURASIP J. Embed. Syst., 2008)

Generating Multi-Threaded code from Polychronous Specifications. - Bijoy Antony Jose; Hiren D. Patel; Sandeep K. Shukla; Jean-Pierre Talpin (SLAP@ETAPS, 2008)

On Cosimulating Multiple Abstraction-Level System-Level Models. - Hiren D. Patel; Sandeep K. Shukla (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A disruptive computer design idea: Architectures with repeatable timing. - Stephen A. Edwards; Sungjun Kim; Edward A. Lee; Isaac Liu; Hiren D. Patel; Martin Schoeberl (ICCD, 2009)

SCGPSim: a fast SystemC simulator on GPUs. - Mahesh Nanjundappa; Hiren D. Patel; Bijoy Antony Jose; Sandeep K. Shukla (ASP-DAC, 2010)

Towards a Multi-MoC Hardware/Software Co-design Framework Using Abstract State Machines. - Nathan Buchanan; Hiren D. Patel (MTV, 2010)

Deploying Hard Real-Time Control Software on Chip-Multiprocessors. - Dai N. Bui; Hiren D. Patel; Edward A. Lee (RTCSA, 2010)

PRET DRAM controller: bank privatization for predictability and temporal isolation. - Jan Reineke 001; Isaac Liu; Hiren D. Patel; Sungjun Kim; Edward A. Lee (CODES+ISSS, 2011)

Temporal isolation on multiprocessing architectures. - Dai N. Bui; Edward A. Lee; Isaac Liu; Hiren D. Patel; Jan Reineke 001 (DAC, 2011)

Abstract state machines as an intermediate representation for high-level synthesis. - Rohit Sinha 001; Hiren D. Patel (DATE, 2011)

Extending Force-Directed Scheduling with Explicit Parallel and Timed Constructs for High-Level Synthesis. - Rohit Sinha 001; Hiren D. Patel (FCCM, 2011)

An authorization scheme for version control systems. - Sitaram Chamarty; Hiren D. Patel; Mahesh V. Tripunitara (SACMAT, 2011)

Robust heterogeneous data center design: a principled approach. - Siddharth Garg; Shreyas Sundaram; Hiren D. Patel (SIGMETRICS Perform. Evaluation Rev., 2011)

Using link-level latency analysis for path selection for real-time communication on NoCs. - Hany Kashif; Hiren D. Patel; Sebastian Fischmeister (ASP-DAC, 2012)

Parallel simulation of mixed-abstraction SystemC models on GPUs and multicore CPUs. - Rohit Sinha 001; Aayush Prakash; Hiren D. Patel (ASP-DAC, 2012)

Reliable computing with ultra-reduced instruction set co-processors. - Aravindkumar Rajendiran; Sundaram Ananthanarayanan; Hiren D. Patel; Mahesh V. Tripunitara; Siddharth Garg (DAC, 2012)

Accelerating SystemC simulations using GPUs. - Mahesh Nanjundappa; Anirudh M. Kaushik; Hiren D. Patel; Sandeep K. Shukla (HLDVT, 2012)

synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs. - Rohit Sinha 001; Hiren D. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Low cost permanent fault detection using ultra-reduced instruction set co-processors. - Sundaram Ananthanarayanan; Siddharth Garg; Hiren D. Patel (DATE, 2013)

On the use of GP-GPUs for accelerating compute-intensive EDA applications. - Valeria Bertacco; Debapriya Chatterjee; Nicola Bombieri; Franco Fummi; Sara Vinco; Anirudh M. Kaushik; Hiren D. Patel (DATE, 2013)

Systemc-clang: An open-source framework for analyzing mixed-abstraction SystemC models. - Anirudh M. Kaushik; Hiren D. Patel (FDL, 2013)

ORTAP: An Offset-based response time analysis for a pipelined communication resource model. - Hany Kashif; Sina Gholamian; Rodolfo Pellizzoni; Hiren D. Patel; Sebastian Fischmeister (IEEE Real-Time and Embedded Technology and Applications Symposium, 2013)

An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture. - Aayush Prakash; Hiren D. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Bounding buffer space requirements for real-time priority-aware networks. - Hany Kashif; Hiren D. Patel (ASP-DAC, 2014)

MEMOCODE 2014 software design contest: Space Invaders emulator. - Stephen A. Edwards; Hiren D. Patel (MEMOCODE, 2014)

A graph associated with the set of all nonzero annihilating ideals of a commutative ring. - Subramanian Visweswaran; Hiren D. Patel (Discret. Math. Algorithms Appl., 2014)

Reliable Computing with Ultra-Reduced Instruction Set Coprocessors. - Dan Wang; Aravindkumar Rajendiran; Sundaram Ananthanarayanan; Hiren D. Patel; Mahesh V. Tripunitara; Siddharth Garg (IEEE Micro, 2014)

Static slack-based instrumentation of programs. - Hany Kashif; Johnson J. Thomas; Hiren D. Patel; Sebastian Fischmeister (ETFA, 2015)

Reverse-engineering embedded memory controllers through latency-based analysis. - Mohamed Hassan 002; Anirudh M. Kaushik; Hiren D. Patel (RTAS, 2015)

A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems. - Mohamed Hassan 002; Hiren D. Patel; Rodolfo Pellizzoni (RTAS, 2015)

SLA: A Stage-Level Latency Analysisfor Real-Time Communicationin a Pipelined Resource Model. - Hany Kashif; Sina Gholamian; Hiren D. Patel (IEEE Trans. Computers, 2015)

MCXplore: An automated framework for validating memory controller designs. - Mohamed Hassan 002; Hiren D. Patel (DATE, 2016)

Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems. - Mohamed Hassan 002; Hiren D. Patel (RTAS, 2016)

Buffer Space Allocation for Real-Time Priority-Aware Networks. - Hany Kashif; Hiren D. Patel (RTAS, 2016)

Path Selection for Real-Time Communication on Priority-Aware NoCs. - Hany Kashif; Hiren D. Patel; Sebastian Fischmeister (ACM Trans. Design Autom. Electr. Syst., 2016)

Applying Models of Computation to OpenCL Pipes for FPGA Computing. - Nachiket Kapre; Hiren D. Patel (IWOCL, 2017)

Predictable Cache Coherence for Multi-core Real-Time Systems. - Mohamed Hassan 002; Anirudh M. Kaushik; Hiren D. Patel (RTAS, 2017)

HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems. - Nivedita Sritharan; Anirudh M. Kaushik; Mohamed Hassan 002; Hiren D. Patel (CoRR, 2017)

PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems. - Mohamed Hassan 002; Hiren D. Patel; Rodolfo Pellizzoni (ACM Trans. Embed. Comput. Syst., 2017)

MCXplore: Automating the Validation Process of DRAM Memory Controller Designs. - Mohamed Hassan 002; Hiren D. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Comparative Study of Predictable DRAM Controllers. - Danlu Guo; Mohamed Hassan 002; Rodolfo Pellizzoni; Hiren D. Patel (ACM Trans. Embed. Comput. Syst., 2018)

Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis. - Mohamed Hassan 002; Anirudh M. Kaushik; Hiren D. Patel (ACM Trans. Embed. Comput. Syst., 2018)

Strengthening PUFs using Composition. - Zhuanhao Wu; Hiren D. Patel; Manoj Sachdev; Mahesh V. Tripunitara (ICCAD, 2019)

CARP: A Data Communication Mechanism for Multi-core Mixed-Criticality Systems. - Anirudh M. Kaushik; Paulos Tegegn; Zhuanhao Wu; Hiren D. Patel (RTSS, 2019)

Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems. - Nivedita Sritharan; Anirudh M. Kaushik; Mohamed Hassan 002; Hiren D. Patel (RTSS, 2019)

On the Task Mapping and Scheduling for DAG-based Embedded Vision Applications on Heterogeneous Multi/Many-core Architectures. - Stefano Aldegheri; Nicola Bombieri; Hiren D. Patel (DATE, 2020)

A Framework for Optimizing CPU-iGPU Communication on Embedded Platforms. - Francesco Lumpp; Hiren D. Patel; Nicola Bombieri (DAC, 2021)

Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols. - Anirudh Mohan Kaushik; Hiren D. Patel (DATE, 2021)

A Systematic Approach to Achieving Tight Worst-Case Latency and High-Performance Under Predictable Cache Coherence. - Anirudh Mohan Kaushik; Hiren D. Patel (RTAS, 2021)

A Hardware Platform for Exploring Predictable Cache Coherence Protocols for Real-time Multicores. - Zhuanhao Wu; Anirudh Mohan Kaushik; Paulos Tegegn; Hiren D. Patel (RTAS, 2021)

Gretch: A Hardware Prefetcher for Graph Analytics. - Anirudh Mohan Kaushik; Gennady Pekhimenko; Hiren D. Patel (ACM Trans. Archit. Code Optim., 2021)

Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems. - Anirudh Mohan Kaushik; Mohamed Hassan 002; Hiren D. Patel (IEEE Trans. Computers, 2021)

Task Mapping and Scheduling for OpenVX Applications on Heterogeneous Multi/Many-Core Architectures. - Francesco Lumpp; Stefano Aldegheri; Hiren D. Patel; Nicola Bombieri (IEEE Trans. Computers, 2021)

Predictable sharing of last-level cache partitions for multi-core safety-critical systems. - Zhuanhao Wu; Hiren D. Patel (DAC, 2022)

Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs. - Srinirdheeshwar Kuttuva Prakash; Hiren D. Patel; Nachiket Kapre (FCCM, 2022)

ZHW: A Numerical CODEC for Big Data Scientific Computation. - Michael Barrow; Zhuanhao Wu; Scott Lloyd; Maya B. Gokhale; Hiren D. Patel; Peter Lindstrom 001 (FPT, 2022)

Containerization and Orchestration of Software for Autonomous Mobile Robots: a Case Study of Mixed-Criticality Tasks across Edge-Cloud Computing Platforms. - Francesco Lumpp; Franco Fummi; Hiren D. Patel; Nicola Bombieri (IROS, 2022)

Enhancing Strong PUF Security with Non-monotonic Response Quantization. - Kleber Stangherlin; Zhuanhao Wu; Hiren D. Patel; Manoj Sachdev (CoRR, 2022)

Design Exploration and Security Assessment of PUF-on-PUF Implementations. - Kleber Stangherlin; Zhuanhao Wu; Hiren D. Patel; Manoj Sachdev (CoRR, 2022)

Secure and Lightweight Strong PUF Challenge Obfuscation with Keyed Non-linear FSR. - Kleber Stangherlin; Zhuanhao Wu; Hiren D. Patel; Manoj Sachdev (CoRR, 2022)

Automatic Construction of Predictable and High-Performance Cache Coherence Protocols for Multicore Real-Time Systems. - Anirudh Mohan Kaushik; Hiren D. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Testchip Measured CRPs of NMQ strong PUF. - Kleber Stangherlin; Zhuanhao Wu; Hiren D. Patel; Manoj Sachdev (IEEE DataPort, 2022)

PASoC: A Predictable Accelerator-rich SoC. - Susmita Tadepalli; Zhuanhao Wu; Hiren D. Patel (CPS-IoT Week Workshops, 2023)

Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems. - Zhuanhao Wu; Marat Bekmyrza; Nachiket Kapre; Hiren D. Patel (DATE, 2023)

SCCL: An open-source SystemC to RTL translator. - Zhuanhao Wu; Maya B. Gokhale; Scott Lloyd; Hiren D. Patel (FCCM, 2023)

ZeroCost-LLC: Shared LLCs at No Cost to WCL. - Zhuanhao Wu; Anirudh M. Kaushik; Hiren D. Patel (RTAS, 2023)

Enhancing Strong PUF Security With Nonmonotonic Response Quantization. - Kleber Stangherlin; Zhuanhao Wu; Hiren D. Patel; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Predictable GPU Wavefront Splitting for Safety-Critical Systems. - Artem Klashtorny; Zhuanhao Wu; Anirudh Mohan Kaushik; Hiren D. Patel (ACM Trans. Embed. Comput. Syst., 2023)

A Compiler Phase to Optimally Split GPU Wavefronts for Safety-Critical Systems. - Artem Klashtorny; Mahesh Tripunitara; Hiren D. Patel (DATE, 2024)

Exclusive Hierarchies for Predictable Sharing in Last-Level Cache. - Xinzhe Wang; Zhuanhao Wu; Rodolfo Pellizzoni; Hiren D. Patel (RTAS, 2024)

Enabling Kubernetes Orchestration of Mixed-Criticality Software for Autonomous Mobile Robots. - Francesco Lumpp; Franco Fummi; Hiren D. Patel; Nicola Bombieri (IEEE Trans. Robotics, 2024)

High Performance and Predictable Shared Last-level Cache for Safety-Critical Systems. - Zhuanhao Wu; Anirudh M. Kaushik; Hiren D. Patel (ACM Trans. Embed. Comput. Syst., 2024)

ARM SVE Unleashed: Performance and Insights Across HPC Applications on Nvidia Grace. - Ruimin Shi; Gabin Schieffer; Maya B. Gokhale; Pei-Hung Lin; Hiren D. Patel; Ivy Peng (Euro-Par (2), 2025)

Consistency-Aware and Predictable Memory Processing for Safety-Critical Out-of-Order Multicores. - Zhuanhao Wu; Hiren D. Patel (RTAS, 2025)