MRAM Cell Technology for Over 500-MHz SoC. - Noboru Sakimura; Tadahiko Sugibayashi; Takeshi Honda; Hiroaki Honjo; Shinsaku Saito; Tetsuhiro Suzuki; Nobuyuki Ishiwata; Shuichi Tahara (IEEE J. Solid State Circuits, 2007)

A 16-Mb Toggle MRAM With Burst Modes. - Tadahiko Sugibayashi; Noboru Sakimura; Takeshi Honda; Kiyokazu Nagahara; Kiyotaka Tsuji; Hideaki Numata; Sadahiko Miura; Ken-ichi Shimura; Yuko Kato; Shinsaku Saito; Yoshiyuki Fukumoto; Hiroaki Honjo; et al. (IEEE J. Solid State Circuits, 2007)

A 90nm 12ns 32Mb 2T1MTJ MRAM. - Ryusuke Nebashi; Noboru Sakimura; Hiroaki Honjo; Shinsaku Saito; Yuichi Ito; Sadahiko Miura; Yuko Kato; Kaoru Mori; Yasuaki Ozaki; Yosuke Kobayashi; Norikazu Ohshima; Keizo Kinoshita; et al. (ISSCC, 2009)

High-speed simulator including accurate MTJ models for spintronics integrated circuit design. - Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Hiroaki Honjo; Tadahiko Sugibayashi; Hiroki Koike; Takashi Ohsawa; Shunsuke Fukami; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (ISCAS, 2012)

A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. - Shoun Matsunaga; Sadahiko Miura; Hiroaki Honjou; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (VLSIC, 2012)

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. - Takashi Ohsawa; Hiroki Koike; Sadahiko Miura; Hiroaki Honjo; Keiichi Tokutome; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (VLSIC, 2012)

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (ISSCC, 2013)

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Hideo Sato; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2013)

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. - Takashi Ohsawa; Hiroki Koike; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (IEEE J. Solid State Circuits, 2013)

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. - Ryusuke Nebashi; Noboru Sakimura; Hiroaki Honjo; Ayuka Morioka; Yukihide Tsuji; Kunihiko Ishihara; Keiichi Tokutome; Sadahiko Miura; Shunsuke Fukami; Keizo Kinoshita; Takahiro Hanyu; Tetsuo Endoh; et al. (ISCAS, 2014)

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. - Noboru Sakimura; Yukihide Tsuji; Ryusuke Nebashi; Hiroaki Honjo; Ayuka Morioka; Kunihiko Ishihara; Keizo Kinoshita; Shunsuke Fukami; Sadahiko Miura; Naoki Kasai; Tetsuo Endoh; Hideo Ohno; et al. (ISSCC, 2014)

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Hideo Sato; Shunsuke Fukami; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (VLSIC, 2015)

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (IEEE J. Solid State Circuits, 2015)

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (ISSCC, 2019)

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (IEEE J. Solid State Circuits, 2019)

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (VLSI Circuits, 2020)

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (IEEE J. Solid State Circuits, 2021)