Modelling and optimization of on-chip spiral inductor in S-parameter domain. - Ken-ichi Okada 001; Hiroaki Hoshino; Hidetoshi Onodera (ISCAS (5), 2004)

A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS. - Hiroaki Hoshino; Ryoichi Tachibana; Toshiya Mitomo; Naoko Ono; Yoshiaki Yoshihara; Ryuichi Fujimoto (ESSCIRC, 2007)

Dynamic Hybrid Type Mining in an Intelligent e-Government Model. - Hiroaki Hoshino; Ning Zhong 001 (Web Intelligence/IAT Workshops, 2007)

A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer. - Toshiya Mitomo; Ryuichi Fujimoto; Naoko Ono; Ryoichi Tachibana; Hiroaki Hoshino; Yoshiaki Yoshihara; Yukako Tsutsumi; Ichiro Seto (IEEE J. Solid State Circuits, 2008)

A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS. - Hiroaki Hoshino; Ryoichi Tachibana; Toshiya Mitomo; Naoko Ono; Yoshiaki Yoshihara; Ryuichi Fujimoto (IEICE Trans. Electron., 2009)

A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications. - Toshiya Mitomo; Naoko Ono; Hiroaki Hoshino; Yoshiaki Yoshihara; Osamu Watanabe 003; Ichiro Seto (IEEE J. Solid State Circuits, 2010)

A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication. - Toshiya Mitomo; Yukako Tsutsumi; Hiroaki Hoshino; Masahiro Hosoya; Tong Wang 018; Yuta Tsubouchi; Ryoichi Tachibana; Akihide Sai; Yuka Kobayashi; Daisuke Kurose; Tomohiko Ito; Koichiro Ban; et al. (ISSCC, 2012)

A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication. - Toshiya Mitomo; Yukako Tsutsumi; Hiroaki Hoshino; Masahiro Hosoya; Tong Wang 018; Yuta Tsubouchi; Ryoichi Tachibana; Akihide Sai; Yuka Kobayashi; Daisuke Kurose; Tomohiko Ito; Koichiro Ban; et al. (IEEE J. Solid State Circuits, 2012)

Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication". - Toshiya Mitomo; Yukako Tsutsumi; Hiroaki Hoshino; Masahiro Hosoya; Tong Wang 018; Yuta Tsubouchi; Ryoichi Tachibana; Akihide Sai; Yuka Kobayashi; Daisuke Kurose; Tomohiko Ito; Koichiro Ban; et al. (IEEE J. Solid State Circuits, 2013)

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication. - Shigehito Saigusa; Toshiya Mitomo; Hidenori Okuni; Masahiro Hosoya; Akihide Sai; Shusuke Kawai; Tong Wang 018; Masanori Furuta; Kei Shiraishi; Koichiro Ban; Seiichiro Horikawa; Tomoya Tandai; et al. (ISSCC, 2014)

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer. - Shusuke Kawai; Hiromitsu Aoyama; Rui Ito; Yutaka Shimizu; Mitsuyuki Ashida; Asuka Maki; Tomohiko Takeuchi; Hiroyuki Kobayashi; Go Urakawa; Hiroaki Hoshino; Shigehito Saigusa; Kazushi Koyama; et al. (ISSCC, 2018)

A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os. - Kosuke Yanagidaira; Mario Sako; Yasuhiro Hirashima; Junya Matsuno; Yumi Higashi; Yutaka Shimizu; Akihiro Imamoto; Kazuaki Kawaguchi; Koji Tabata; Takeshi Nakano; Yusuke Ochi; Hiroaki Hoshino; et al. (ISSCC, 2025)