A 32-Bit CMOS Microprocessor with Six-Stage Pipeline Structure. - Hiroaki Kaneko; Y. Miki; S. Nohara; K. Koya; M. Araki (FJCC, 1986)

A 6.7-MFLOPS floating-point coprocessor with vector/matrix instructions. - Takashi Nakayama; Hisao Harigai; Shingo Kojima; Hiroaki Kaneko; Hatsuhide Igarashi; Tsuneo Toba; Yutaka Yamagami; Yoichi Yano (IEEE J. Solid State Circuits, 1989)

Prototype instrument for sheet resistance measurement by pulse voltage excitation. - Hideo Saotome; Hiroaki Kaneko (ICST, 2013)

An integrated machine code monitor for a RISC-V processor on an FPGA. - Hiroaki Kaneko; Akinori Kanasugi (Artif. Life Robotics, 2020)