SP2: A Very Large-Scale Event Driven Logic Simulation Hardware. - Hirofumi Hamamura; Hiroaki Komatsu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor. - Noriyuki Ito; Hiroaki Komatsu; Yoshiyasu Tanamura; Ryoichi Yamashita; Hiroyuki Sugiyama; Yaroku Sugiyama; Hirofumi Hamamura (ICCD, 2003)

Detection of multiple transitions in delay fault test of SPARC64 microprocessor. - Daisuke Maruyama; Akira Kanuma; Takashi Mochiyama; Hiroaki Komatsu; Yaroku Sugiyama; Noriyuki Ito (ICCAD, 2004)

Diagonal routing in high performance microprocessor design. - Noriyuki Ito; Hideaki Katagiri; Ryoichi Yamashita; Hiroshi Ikeda; Hiroyuki Sugiyama; Hiroaki Komatsu; Yoshiyasu Tanamura; Akihiro Yoshitake; Kazuhiro Nonomura; Kinya Ishizaka; Hiroaki Adachi; Yutaka Mori; et al. (ASP-DAC, 2006)

Design Methodology for 2.4GHz Dual-Core Microprocessor. - Noriyuki Ito; Hiroaki Komatsu; Akira Kanuma; Akihiro Yoshitake; Yoshiyasu Tanamura; Hiroyuki Sugiyama; Ryoichi Yamashita; Ken-ichi Nabeya; Hironobu Yoshino; Hitoshi Yamanaka; Masahiro Yanagida; Yoshitomo Ozeki; et al. (ASP-DAC, 2007)

Speed-path analysis for multi-path failed latches with random variation. - Tsutomu Ishida; Izumi Nitta; Katsumi Homma; Yuzi Kanazawa; Hiroaki Komatsu (ISQED, 2012)