A 33-ns 64-Mb DRAM. - Yukihito Oowaki; Kenji Tsuchida; Yohji Watanabe; Daisaburo Takashima; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Akihiro Nitayama; Fumio Horiguchi; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1991)

Word-line architecture for highly reliable 64-Mb DRAM. - Daisaburo Takashima; Yukihito Oowaki; Ryu Ogiwara; Yohji Watanabe; Kenji Tsuchida; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1992)

Open/folded bit-line arrangement for ultra-high-density DRAM's. - Daisaburo Takashima; Shigeyoshi Watanabe; Hiroaki Nakano; Yukihito Oowaki; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1994)

Block jam. - Henry Newton Dunn; Hiroaki Nakano; James Gibson (SIGGRAPH Abstracts and Applications, 2002)

A cell transistor scalable DRAM array architecture. - Daisaburo Takashima; Hiroaki Nakano (IEEE J. Solid State Circuits, 2002)

A centralized storage system with automated data tiering for private cloud environment. - Mikifumi Shikida; Hiroaki Nakano; Shuichi Kozaka; Masato Mato; Satoshi Uda (SIGUCCS, 2013)

A call for champions: why some 'history of computing' courses are more successful than others. - Hiroaki Nakano; Matthew G. Styles; Geoffrey M. Draper (Inroads, 2013)

Graphical narrative interfaces: Representing spatiotemporal information for a highly autonomous human-robot team. - Hiroaki Nakano; Michael A. Goodrich (RO-MAN, 2015)

The impact of first metatarsophalangeal angle on the gait features measured by an in-shoe motion sensor. - Chenhui Huang; Kenichiro Fukushi; Zhenwei Wang 001; Hiroshi Kajitani; Hannah Pokka; Hiroko Narasaki; Fumiyuki Nihey; Hiroaki Nakano; Kentaro Nakahara (IEEE SENSORS, 2020)