A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. - Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Masatoshi Ishikawa; Toshihiro Inokuchi; Hiroshi Kato; Hiroaki Tanizaki; Wataru Abe; Akinori Shibayama; Yoshifumi Fukushima; Mitsutaka Niiro; Masanao Maruta; et al. (IEEE J. Solid State Circuits, 2001)

A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test. - Shigeki Tomishima; Hiroaki Tanizaki; Mitsutaka Niiro; Masanao Maruta; Hideto Hidaka; T. Tada; Kenji Gamo (ITC, 2002)

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. - Hirohito Kikukawa; Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Shouji Sakamoto; Masatoshi Ishikawa; Wataru Abe; Hiroaki Tanizaki; Hiroshi Kato; Toshitaka Uchikoba; Toshihiro Inokuchi; Manabu Senoh; et al. (IEEE J. Solid State Circuits, 2002)

Formalization and Consistency Checking of Changes of Software System Configurations Using Alloy. - Hiroaki Tanizaki; Takuya Katayama (APSEC, 2008)

A Variability Management Method for Software Configuration Files. - Hiroaki Tanizaki; Toshiaki Aoki; Takuya Katayama (SEKE, 2012)

A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications. - Masanori Hayashikoshi; Hiroaki Tanizaki; Yasumitsu Murai; Takaharu Tsuji; Kiyoshi Kawabata; Koji Nii; Hideyuki Noda; Hiroyuki Kondo; Yoshio Matsuda; Hideto Hidaka (IEICE Trans. Electron., 2019)