Circuit Simulation Models for Coming MOSFET Generations. - Mitiko Miura-Mattausch; Hiroaki Ueno; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design. - Kazuya Hisamitsu; Hiroaki Ueno; Masayasu Tanaka; Daisuke Kitamaru; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (ASP-DAC, 2003)

1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation. - Shizunori Matsumoto; Hiroaki Ueno; Satoshi Hosokawa; Toshihiko Kitamura; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ohguro; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Electron., 2005)

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential. - Dondee Navarro; Takeshi Mizoguchi; Masami Suetake; Kazuya Hisamitsu; Hiroaki Ueno; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Electron., 2005)

30.5 A GaN 3×3 matrix converter chipset with Drive-by-Microwave technologies. - Shuichi Nagai; Yasuhiro Yamada; Noboru Negoro; Hiroyuki Handa; Yuji Kudoh; Hiroaki Ueno; Masahiro Ishida; Nobuyuki Otuska; Daisuke Ueda (ISSCC, 2014)