A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. - Hiroaki Yamaoka; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2001)

Logic synthesis for PLA with 2-input logic elements. - Hiroaki Yoshida; Hiroaki Yamaoka; Makoto Ikeda; Kunihiro Asada (ISCAS (3), 2002)

Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. - Hiroaki Yoshida; Hiroaki Yamaoka; Makoto Ikeda; Kunihiro Asada (ASP-DAC/VLSI Design, 2002)

A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design. - Hiroaki Yamaoka; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2003)

A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells. - Ulkuhan Ekinciel; Hiroaki Yamaoka; Hiroaki Yoshida; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Inf. Syst., 2005)