High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit. - Katsuyuki Ochiai; Hiroe Iwasaki; Jiro Naganuma; Makoto Endo; Takeshi Ogura (DATE, 1999)

On-Chip Multimedia Real-Time OS and its MPEG-2 Applications. - Hiroe Iwasaki; Jiro Naganuma; Makoto Endo; Takeshi Ogura (RTCSA, 1999)

SuperENC: MPEG-2 video encoder chip. - Mitsuo Ikeda; Toshio Kondo; Koyo Nitta; Kazuhito Suguri; Takeshi Yoshitome; Toshihiro Minami; Hiroe Iwasaki; Katsuyuki Ochiai; Jiro Naganuma; Makoto Endo; Yutaka Tashiro; Hiroshi Watanabe 005; et al. (IEEE Micro, 1999)

Advanced concurrent design environment for multimedia system LSIs. - Hiroe Iwasaki; Katsuyuki Ochiai; Jiro Naganuma; Makoto Endo; Takeshi Ogura (Syst. Comput. Jpn., 2002)

A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems. - Hiroe Iwasaki; Jiro Naganuma; Yasuyuki Nakajima; Yutaka Tashiro; Ken Nakamura; Takeshi Yoshitome; Takayuki Onishi; Mitsuo Ikeda; Takaaki Izuoka; Makoto Endo (CICC, 2003)

Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. - Hiroe Iwasaki; Jiro Naganuma; Koyo Nitta; Ken Nakamura; Takeshi Yoshitome; Mitsuo Ogura; Yasuyuki Nakajima; Yutaka Tashiro; Takayuki Onishi; Mitsuo Ikeda; Makoto Endo (DATE, 2003)

MPEG-2 real-time software CODEC for full-duplex transmission application over IP networks. - Hiroe Iwasaki; Jiro Naganuma; Makoto Endo; Yoshiyuki Yashima (Syst. Comput. Jpn., 2005)

New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex CODEC LSI. - Minoru Inamori; Hiroe Iwasaki; Takayuki Onishi; Mitsuo Ikeda; Jiro Naganuma; Yoshiyuki Yashima (IEEE Trans. Consumer Electron., 2005)

Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level. - Hiroe Iwasaki; Jiro Naganuma; Koyo Nitta; Ken Nakamura; Takeshi Yoshitome; Mitsuo Ogura; Yasuyuki Nakajima; Yutaka Tashiro; Takayuki Onishi; Mitsuo Ikeda; Toshihiro Minami; Makoto Endo; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2007)

MVC real-time video encoder for full-HDTV 3D video. - Mitsuo Ikeda; Takayuki Onishi; Takashi Sano 001; Atsushi Sagata; Hiroe Iwasaki; Yasuyuki Nakajima; Koyo Nitta; Yasuko Takahashi; Kazuya Yokohari; Daisuke Kobayashi; Kazuto Kamikura; Hirohisa Jozawa (ICCE, 2012)

An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures. - Koyo Nitta; Hiroe Iwasaki; Takayuki Onishi; Takashi Sano 001; Atsushi Sagata; Yasuyuki Nakajima; Minoru Inamori; Ryuichi Tanida; Atsushi Shimizu; Ken Nakamura; Mitsuo Ikeda; Jiro Naganuma (IEICE Trans. Electron., 2012)

Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure. - Hiroe Iwasaki; Takayuki Onishi; Ken Nakamura; Koyo Nitta; Takashi Sano 001; Yukikuni Nishida; Kazuya Yokohari; Jia Su; Naoki Ono; Ritsu Kusaba; Atsushi Sagata; Mitsuo Ikeda; et al. (Hot Chips Symposium, 2015)

Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability. - Takayuki Onishi; Takashi Sano 001; Yukikuni Nishida; Kazuya Yokohari; Jia Su; Ken Nakamura; Koyo Nitta; Kimiko Kawashima; Jun Okamoto; Naoki Ono; Ritsu Kusaba; Atsushi Sagata; et al. (VLSIC, 2015)

An HEVC real-time encoding system with high quality HDR color representations. - Daisuke Kobayashi; Ken Nakamura; Takayuki Onishi; Yasuyuki Nakajima; Hiroe Iwasaki; Mitsuo Ikeda; Atsushi Shimizu (ICCE, 2018)

A 4K/60p HEVC Real-Time Encoding System With High Quality HDR Color Representations. - Daisuke Kobayashi; Ken Nakamura; Takayuki Onishi; Hiroe Iwasaki; Atsushi Shimizu (IEEE Trans. Consumer Electron., 2018)

A 120 fps High Frame Rate Real-time HEVC Video Encoder with Parallel Configuration Scalable to 4K. - Yuya Omori; Takayuki Onishi; Hiroe Iwasaki; Atsushi Shimizu (IEEE Trans. Multi Scale Comput. Syst., 2018)

A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K. - Takayuki Onishi; Takashi Sano 001; Yukikuni Nishida; Kazuya Yokohari; Ken Nakamura; Koyo Nitta; Kimiko Kawashima; Jun Okamoto; Naoki Ono; Atsushi Sagata; Hiroe Iwasaki; Mitsuo Ikeda; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. - Ken Nakamura; Yuya Omori; Daisuke Kobayashi; Tatsuya Osawa; Takayuki Onishi; Koyo Nitta; Hiroe Iwasaki; Atsushi Shimizu (COOL CHIPS, 2019)

A Real-Time 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control. - Daisuke Kobayashi; Ken Nakamura; Tatsuya Osawa; Yuya Omori; Takayuki Onishi; Hiroe Iwasaki (GLOBECOM, 2019)

4K 120fps HEVC Temporal Scalable Encoder with Super Low Delay. - Yuya Omori; Ken Nakamura; Takayuki Onishi; Daisuke Kobayashi; Tatsuya Osawa; Hiroe Iwasaki (ICECS, 2019)

A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation. - Takayuki Onishi; Yuya Omori; Ken Nakamura; Hiroe Iwasaki; Atsushi Shimizu (ISCAS, 2019)

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. - Ken Nakamura; Daisuke Kobayashi; Yuya Omori; Tatsuya Osawa; Takayuki Onishi; Koyo Nitta; Hiroe Iwasaki (IEICE Trans. Electron., 2020)

4K 120fps HEVC Encoder with Multi-Chip Configuration. - Yuya Omori; Ken Nakamura; Takayuki Onishi; Daisuke Kobayashi; Tatsuya Osawa; Hiroe Iwasaki (IEICE Trans. Commun., 2021)

An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture. - Ken Nakamura; Yuya Omori; Daisuke Kobayashi; Koyo Nitta; Kimikazu Sano; Masayuki Sato 001; Hiroe Iwasaki; Hiroaki Kobayashi (COOL CHIPS, 2022)

OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Hiroe Iwasaki; Daisuke Kobayashi; Yuya Omori; Ken Nakamura; Koyo Nitta; Kimikazu Sano (MWSCAS, 2022)

A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders. - Masayuki Sato 001; Yuya Omori; Ryusuke Egawa; Ken Nakamura; Daisuke Kobayashi; Hiroe Iwasaki; Kazuhiko Komatsu; Hiroaki Kobayashi (PDCAT, 2022)

A Low-Latency 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control for Live Streaming. - Daisuke Kobayashi; Ken Nakamura; Masaki Kitahara; Tatsuya Osawa; Yuya Omori; Takayuki Onishi; Hiroe Iwasaki (IEICE Trans. Inf. Syst., 2023)

An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture. - Ken Nakamura; Yuya Omori; Daisuke Kobayashi; Koyo Nitta; Kimikazu Sano; Masayuki Sato 001; Hiroe Iwasaki; Hiroaki Kobayashi (IEICE Trans. Electron., 2023)

Adaptive Parallelization based on Frame-level and Tile-level Parallelisms for VVC Encoding. - Karin Onouchi; Masayuki Sato 001; Hiroe Iwasaki; Kazuhiko Komatsu; Hiroaki Kobayashi (CANDAR, 2024)

ISP Parameter Optimization and FPGA Implementation for Object Detection in Low-Light Conditions. - Kento Mishima; Naoya Niwa; Kazutoshi Wakabayashi; Hiroe Iwasaki (COOL CHIPS, 2024)

Picture Partitioning Design of Neural Network-Based Intra Coding For Video Coding For Machines. - Keiichi Chono; Naoya Niwa; Hiroe Iwasaki (ICIP, 2024)

An Ising-based Decision Method for Intra Prediction Mode in Video Coding. - Takuto Momominami; Naoya Niwa; Masahito Kumagai; Kazuhiko Komatsu; Hiroaki Kobayashi; Hiroe Iwasaki (SC Workshops, 2024)

A Fast Block Partitioning Decision Method Using Luminance Textures for VVC Encoders. - Rikita Uchiyama; Karin Onouchi; Naoya Niwa; Masayuki Sato 001; Hiroaki Kobayashi; Hiroe Iwasaki (ICCE, 2025)