A 5-ns GaAs 16-kb SRAM. - Shuichi Matsue; Hiroshi Makino; Minoru Noda; Hirofumi Nakano; Satoshi Takano; Kazuo Nishitani; Shimpei Kayano (IEEE J. Solid State Circuits, 1991)

The reversible DNA-alkylating activity of duocarmycin and its analogues. - Akira Asai; Satoru Nagamura; Hiromitsu Saito; Isami Takahashi; Hirofumi Nakano (Nucleic Acids Res., 1994)

A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure. - Akira Ohta; Norio Higashisaka; Tetsuya Heima; Takayuki Hisaka; Hirofumi Nakano; Ryuji Ohmura; Tadashi Takagi; Noriyuki Tanino (IEEE J. Solid State Circuits, 1999)

Bolt Tightening Using Impact Wrench Based on Neural Networks. - Toru Fujinaka; Hirofumi Nakano; Michifumi Yoshioka; Sigeru Omatu 001 (J. Robotics Mechatronics, 2000)

Bolt tightening control using neural networks. - Toru Fujinaka; Hirofumi Nakano; Sigeru Omatu 001 (SMC, 2001)

Multigrain Automatic Parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler. - Hironori Kasahara; Motoki Obata; Kazuhisa Ishizaka; Keiji Kimura; Hiroki Kaminaga; Hirofumi Nakano; Kouhei Nagasawa; Akiko Murai; Hiroki Itagaki; Jun Shirako (PARELEC, 2002)

Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP. - Hirofumi Nakano; Kazuhisa Ishizaka; Motoki Obata; Keiji Kimura; Hironori Kasahara (Int. J. Parallel Program., 2003)

Multigrain parallel processing on compiler cooperative chip multiprocessor. - Keiji Kimura; Yasutaka Wada; Hirofumi Nakano; Takeshi Kodaka; Jun Shirako; Kazuhisa Ishizaka; Hironori Kasahara (Interaction between Compilers and Computer Architectures, 2005)

Performance Evaluation of Compiler Controlled Power Saving Scheme. - Jun Shirako; Munehiro Yoshida; Naoto Oshiyama; Yasutaka Wada; Hirofumi Nakano; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (ISHPC, 2005)

Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API. - Takamichi Miyamoto; Saori Asaka; Hiroki Mikami; Masayoshi Mase; Yasutaka Wada; Hirofumi Nakano; Keiji Kimura; Hironori Kasahara (ISPA, 2008)

Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. - Koji Nii; Makoto Yabuuchi; Hidehiro Fujiwara; Hirofumi Nakano; Kazuya Ishihara; Hiroyuki Kawai; Kazutami Arimoto (SoCC, 2010)

A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture. - Yasutaka Wada; Akihiro Hayashi; Takeshi Masuura; Jun Shirako; Hirofumi Nakano; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (Trans. High Perform. Embed. Archit. Compil., 2011)

A stable chip-ID generating physical uncloneable function using random address errors in SRAM. - Hidehiro Fujiwara; Makoto Yabuuchi; Yasumasa Tsukamoto; Hirofumi Nakano; Toru Owada; Hiroyuki Kawai; Koji Nii (SoCC, 2012)

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. - Yohei Nakata; Yuta Kimi; Shunsuke Okumura; Jinwook Jung; Takuya Sawada; Taku Toshikawa; Makoto Nagata; Hirofumi Nakano; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Hiroyuki Kawai; et al. (ISQED, 2014)

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. - Yohei Nakata; Yuta Kimi; Shunsuke Okumura; Jinwook Jung; Takuya Sawada; Taku Toshikawa; Makoto Nagata; Hirofumi Nakano; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Hiroyuki Kawai; et al. (IEICE Trans. Electron., 2014)

Theoretical Analysis of Activity Cliffs among Benzofuranone-Class Pim1 Inhibitors Using the Fragment Molecular Orbital Method with Molecular Mechanics Poisson-Boltzmann Surface Area (FMO+MM-PBSA) Approach. - Chiduru Watanabe; Hirofumi Watanabe; Kaori Fukuzawa; Lorien J. Parker; Yoshio Okiyama; Hitomi Yuki; Shigeyuki Yokoyama; Hirofumi Nakano; Shigenori Tanaka; Teruki Honma (J. Chem. Inf. Model., 2017)