A 24-b 50-ns digital image signal processor. - Shin-ichi Nakagawa; Hideyuki Terane; Tetsuya Matsumura; Hiroshi Segawa; Masahiko Yoshimoto; Hirofumi Shinohara; Shuichi Kato; Masahiro Hatanaka; Hideo Ohira; Yoshiaki Kato; Mamoru Iwatsuki; Kinya Tabuchi; et al. (IEEE J. Solid State Circuits, 1990)

A flexible multiport RAM compiler for data path. - Hirofumi Shinohara; Noriaki Matsumoto; Kumiko Fujimori; Yoshiki Tsujihashi; Hiroomi Nakao; Shuichi Kato; Yasutaka Horiba; Akiharu Tada (IEEE J. Solid State Circuits, 1991)

A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses. - Yutaka Arima; Mitsuhiro Murasaki; Tsuyoshi Yamada; Atsushi Maeda; Hirofumi Shinohara (IEEE J. Solid State Circuits, 1992)

A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. - Hiroshi Makino; Yasunobu Nakase; Hirofumi Shinohara (ICCD, 1993)

A BiCMOS wired-OR logic. - Yasunobu Nakase; Hiroaki Suzuki; Hiroshi Makino; Hirofumi Shinohara; Koichiro Mashiko (IEEE J. Solid State Circuits, 1995)

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. - Hiroshi Makino; Yasunobu Nakase; Hiroaki Suzuki; Hiroyuki Morinaka; Hirofumi Shinohara; Koichiro Mashiko (IEEE J. Solid State Circuits, 1996)

A 64-bit carry look ahead adder using pass transistor BiCMOS gates. - Kiniio Ueda; Hiroaki Suzuki; Kakutaro Suda; Hirofumi Shinohara; Koichiro Mashiko (IEEE J. Solid State Circuits, 1996)

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. - Yasumasa Tsukamoto; Koji Nii; Susumu Imaoka; Yuji Oda; Shigeki Ohbayashi; Tomoaki Yoshizawa; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara (ICCAD, 2005)

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. - Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; et al. (ISSCC, 2007)

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. - Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (ISSCC, 2007)

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. - Shigeki Ohbayashi; Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Susumu Imaoka; Yuji Oda; Tsutomu Yoshihara; Motoshige Igarashi; Masahiko Takeuchi; Hiroshi Kawashima; Yasuo Yamaguchi; Kazuhiro Tsukamoto; et al. (IEEE J. Solid State Circuits, 2007)

Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling. - Masanori Kurimoto; Hiroaki Suzuki; Rei Akiyama; Tadao Yamanaka; Haruyuki Ohkuma; Hidehiro Takata; Hirofumi Shinohara (DAC, 2008)

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. - Masako Fujii; Hiroaki Suzuki; Hiromi Notani; Hiroshi Makino; Hirofumi Shinohara (ESSCIRC, 2008)

Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. - Hiroaki Suzuki; Masanori Kurimoto; Tadao Yamanaka; Hidehiro Takata; Hiroshi Makino; Hirofumi Shinohara (ISLPED, 2008)

A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology. - Masako Fujii; Koji Nii; Hiroshi Makino; Shigeki Ohbayashi; Motoshige Igarashi; Takeshi Kawamura; Miho Yokota; Nobuhiro Tsuda; Tomoaki Yoshizawa; Toshikazu Tsutsui; Naohiko Takeshita; Naofumi Murata; et al. (IEICE Trans. Electron., 2008)

Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration. - Hirofumi Shinohara; Koji Nii; Hidetoshi Onodera (IEICE Trans. Electron., 2008)

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. - Satoshi Ishikura; Marefusa Kurumada; Toshio Terano; Yoshinobu Yamagami; Naoki Kotani; Katsuji Satomi; Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Toshiyuki Oashi; Hiroshi Makino; et al. (IEEE J. Solid State Circuits, 2008)

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. - Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (IEEE J. Solid State Circuits, 2008)

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. - Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; et al. (IEEE J. Solid State Circuits, 2008)

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. - Koji Nii; Yasumasa Tsukamoto; Makoto Yabuuchi; Yasuhiro Masuda; Susumu Imaoka; Keiichi Usui; Shigeki Ohbayashi; Hiroshi Makino; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2009)

0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. - Toshikazu Suzuki; Shinichi Moriwaki; Atsushi Kawasumi; Shinji Miyano; Hirofumi Shinohara (ESSCIRC, 2010)

Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling. - Masanori Kurimoto; Hiroaki Suzuki; Rei Akiyama; Tadao Yamanaka; Haruyuki Ohkuma; Hidehiro Takata; Hirofumi Shinohara (ACM Trans. Design Autom. Electr. Syst., 2010)

A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates. - Hiroshi Fuketa; Satoshi Iida; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (DAC, 2011)

12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. - Atsushi Muramatsu; Tadashi Yasufuku; Masahiro Nomura; Makoto Takamiya; Hirofumi Shinohara; Takayasu Sakurai (ESSCIRC, 2011)

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics. - Hiroshi Fuketa; Koji Hirairi; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (ISLPED, 2011)

Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. - Yu Pu; Xin Zhang 025; Katsuyuki Ikeuchi; Atsushi Muramatsu; Atsushi Kawasumi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. - Hiroshi Fuketa; Ryo Takahashi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (CICC, 2012)

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. - Yasue Yamamoto; Atsushi Kawasumi; Shinichi Moriwaki; Toshikazu Suzuki; Shinji Miyano; Hirofumi Shinohara (ESSCIRC, 2012)

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits. - Tadashi Yasufuku; Koji Hirairi; Yu Pu; Yun Fei Zheng; Ryo Takahashi; Masato Sasaki; Hiroshi Fuketa; Atsushi Muramatsu; Masahiro Nomura; Hirofumi Shinohara; Makoto Takamiya; Takayasu Sakurai (ISQED, 2012)

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. - Koji Hirairi; Yasuyuki Okuma; Hiroshi Fuketa; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (ISSCC, 2012)

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. - Shinichi Moriwaki; Yasuhiro Yamamoto; Atsushi Kawasumi; Toshikazu Suzuki; Shinji Miyano; Takayasu Sakurai; Hirofumi Shinohara (VLSIC, 2012)

Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. - Ryo Takahashi; Hidehiro Takata; Tadashi Yasufuku; Hiroshi Fuketa; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Variation-aware subthreshold logic circuit design. - Hiroshi Fuketa; Ryo Takahashi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (ASICON, 2013)

A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. - Shusuke Yoshimoto; Shinji Miyano; Makoto Takamiya; Hirofumi Shinohara; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2013)

Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. - Hiroshi Fuketa; Ryo Takahashi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE J. Solid State Circuits, 2013)

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. - Shinji Miyano; Shinichi Moriwaki; Yasue Yamamoto; Atsushi Kawasumi; Toshikazu Suzuki; Takayasu Sakurai; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2013)

Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique. - Hiroshi Fuketa; Koji Hirairi; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. - Koichiro Ishibashi; Nobuyuki Sugii; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham; Hideki Makiyama; Yoshiki Yamamoto; Hirofumi Shinohara; Toshiaki Iwamatsu; Yasuo Yamaguchi; Hidekazu Oda; et al. (COOL Chips, 2014)

Extremely Low Power Digital and Analog Circuits. - Hirofumi Shinohara (IEICE Trans. Electron., 2014)

Design of a Sensorless Controller Synthesized by Robust H∞ Control for Boost Converters. - Xutao Li; Minjie Chen; Hirofumi Shinohara; Tsutomu Yoshihara (IEICE Trans. Commun., 2016)

A 3.5ppm/°C 0.85V Bandgap Reference Circuit without Resistors. - Jing Wang; Qiang Li; Li Ding; Hirofumi Shinohara; Yasuaki Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Analysis and reduction of SRAM PUF Bit Error Rate. - Hirofumi Shinohara; Baikun Zheng; Yanhao Piao; Bo Liu; Shiyu Liu (VLSI-DAT, 2017)

Accurate Nanopower Supply-Insensitive CMOS Unit Vth Extractor and αVth Extractor with Continuous Variety. - Jing Wang; Li Ding; Qiang Li; Hirofumi Shinohara; Yasuaki Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A 373 F2 2D Power-Gated EE SRAM Physically Unclonable Function With Dark-Bit Detection Technique. - Kunyang Liu; Yue Min; Xuan Yang; Hanfeng Sun; Hirofumi Shinohara (A-SSCC, 2018)

High-throughput Von Neumann post-processing for random number generator. - Ruilin Zhang; Sijia Chen; Chao Wan; Hirofumi Shinohara (VLSI-DAT, 2018)

A CMOS 0.85-V 15.8-nW Current and Voltage Reference without Resistors. - Jing Wang; Hirofumi Shinohara (VLSI-DAT, 2019)

A 0.5-V 2.07-fJ/b 497-F2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in. - Kunyang Liu; Hongliang Pu; Hirofumi Shinohara (CICC, 2020)

An Inverter-Based True Random Number Generator with 4-bit Von-Neumann Post-Processing Circuit. - Xingyu Wang 002; Hongjie Liu; Ruilin Zhang; Kunyang Liu; Hirofumi Shinohara (MWSCAS, 2020)

A 373-F2 0.21%-Native-BER EE SRAM Physically Unclonable Function With 2-D Power-Gated Bit Cells and ${V}_{ text{SS}}$ Bias-Based Dark-Bit Detection. - Kunyang Liu; Yue Min; Xuan Yang; Hanfeng Sun; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2020)

36.3 A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate Through In-Cell Hot-Carrier Injection Burn-In. - Kunyang Liu; Zihan Fu; Gen Li; Hongliang Pu; Zhibo Guan; Xingyu Wang 002; Xinpeng Chen; Hirofumi Shinohara (ISSCC, 2021)

Session 36 Overview: Hardware Security Digital Architectures and Systems Subcommittee. - Hirofumi Shinohara; Massimo Alioto; Ingrid Verbauwhede (ISSCC, 2021)

A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement. - Ruilin Zhang; Xingyu Wang 002; Luying Wang; Xinpeng Chen; Fan Yang; Kunyang Liu; Hirofumi Shinohara (VLSI Circuits, 2021)

A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement. - Kunyang Liu; Xinpeng Chen; Hongliang Pu; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2021)

A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical Performance. - Kunyang Liu; Gen Li; Zihan Fu; Xuanzhen Wang; Hirofumi Shinohara (ESSCIRC, 2022)

A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement. - Xingyu Wang 002; Ruilin Zhang; Yuxin Wang; Kunyang Liu; Xuanzhen Wang; Hirofumi Shinohara (VLSI-DAT, 2022)

A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement. - Ruilin Zhang; Xingyu Wang 002; Kunyang Liu; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2022)

A 100-Bit-Output Modeling Attack-Resistant SPN Strong PUF with Uniform and High-Randomness Response. - Kunyang Liu; Yichen Tang; Shufan Xu; Ruilin Zhang; Hirofumi Shinohara (CICC, 2023)

Practical Markov Chain and Von Neumann based Post-processing Circuits for True Random Number Generators. - Ruilin Zhang; Haochen Zhang; Xingyu Wang 002; Ziyang Ye; Kunyang Liu; Hirofumi Shinohara (MWSCAS, 2023)

SpongePUF: A Modeling Attack Resilient Strong PUF with Scalable Challenge Response Pair. - Zhenzhe Chen; Takashi Sato; Hirofumi Shinohara (HOST, 2024)

CLAPPER: Clonable LFSR-based Asymmetric PUF-group with Peer-to-peer Equivalent Response. - Zhenzhe Chen; Kunyang Liu; Hirofumi Shinohara; Takashi Sato (MWSCAS, 2024)

A 0.00027 mm2 1.2V 0.089pJ/bit 10Gbps 41.6 GHz Standard-Cell-Based Passive-Less Wireless OOK Transmitter with On-Chip Antenna in 12nm FinFET. - Hiroaki Kitaike; Hironori Tagawa; Masaya Kaneko; Jin Nakamura; Shufan Xu; Ruilin Zhang; Kunyang Liu; Hiroki Wakatsuchi; Kyoya Takano; Hirofumi Shinohara; Kiichi Niitsu (NorCAS, 2024)

A 2 Hz, 1.2-2 V, 0.22-9 nW, 0.007 mm2 65 nm CMOS Multiple- Output Down-Converter-Less Clock Generator Using Stacked an Oscillator and Frequency Dividers for Scaling-Friendly IoTs. - You Wu; Kei Awano; Kento Okamura; Teruaki Ono; Kohei Sakamoto; Hiroaki Kitaike; Hironori Tagawa; Jin Nakamura; Masaya Kaneko; Yuta Kimura; Hiroaki Nakamura; Shufan Xu; et al. (NorCAS, 2024)

A Single-Inverter-Based True Random Number Generator with On-Chip Clock-Tuning-Based Entropy Calibration Circuit. - Xingyu Wang; Ruilin Zhang; Hirofumi Shinohara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement. - Xingyu Wang 002; Ruilin Zhang; Kunyang Liu; Hirofumi Shinohara (IEEE Trans. Very Large Scale Integr. Syst., 2024)

De-Correlation and De-Bias Post-Processing Circuits for True Random Number Generator. - Ruilin Zhang; Haochen Zhang; Xingyu Wang 002; Ziyang Ye; Kunyang Liu; Shinichi Nishizawa; Kiichi Niitsu; Hirofumi Shinohara (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 22 nm CMOS 0.034 mm2 0.4 V 1.3 nW Frequency-Recording IC with 400-Bit Data-Storing Shift Registers Using Burst-Pulse Counting and Reference Pulse Generation for Stand-Alone Continuous Glucose Monitoring Contact Lenses. - Kei Awano; You Wu; Kento Okamura; Teruaki Ono; Kohei Sakamoto; Hiroaki Kitaike; Hironori Tagawa; Jin Nakamura; Masaya Kaneko; Yuta Kimura; Hiroaki Nakamura; Shufan Xu; et al. (LASCAS, 2025)

A 22 nm CMOS .000005 text{mm}^{2} 0.25 mathrm{V}$ 2.3pW ISFET Front-End Using Low-Gate-Leakage Thick-Gate-Oxide Transistors for Energy-Efficient Small-Formfactor pH Monitoring. - Hiroaki Kitaike; Ruilin Zhang; Hironori Tagawa; Kento Okamura; Kei Awano; You Wu; Teruaki Ono; Kohei Sakamoto; Jin Nakamura; Masaya Kaneko; Kunyang Liu; Shufan Xu; et al. (NewCAS, 2025)