A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. - Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Masatoshi Ishikawa; Toshihiro Inokuchi; Hiroshi Kato; Hiroaki Tanizaki; Wataru Abe; Akinori Shibayama; Yoshifumi Fukushima; Mitsutaka Niiro; Masanao Maruta; et al. (IEEE J. Solid State Circuits, 2001)

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. - Hirohito Kikukawa; Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Shouji Sakamoto; Masatoshi Ishikawa; Wataru Abe; Hiroaki Tanizaki; Hiroshi Kato; Toshitaka Uchikoba; Toshihiro Inokuchi; Manabu Senoh; et al. (IEEE J. Solid State Circuits, 2002)

A 400-MHz random-cycle dual-port interleaved DRAM (D2RAM) with standard CMOS Process. - Masanori Shirahama; Yasuhiro Agata; Toshiaki Kawasaki; Ryuji Nishihara; Wataru Abe; Naoki Kuroda; Hiroyuki Sadakata; Toshitaka Uchikoba; Kazunari Takahashi; Kyoko Egashira; Shinji Honda; Miho Miura; et al. (IEEE J. Solid State Circuits, 2005)

A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI. - Yasue Yamamoto; Masanori Shirahama; Toshiaki Kawasaki; Ryuji Nishihara; Shinichi Sumi; Yasuhiro Agata; Hirohito Kikukawa; Hiroyuki Yamauchi (IEICE Trans. Electron., 2007)