Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. - Akira Mochizuki; Takeshi Kitamura; Hirokatsu Shirahama; Takahiro Hanyu (ISMVL, 2006)

Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic. - Akira Mochizuki; Hirokatsu Shirahama; Takahiro Hanyu (IEICE Trans. Electron., 2006)

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. - Hirokatsu Shirahama; Akira Mochizuki; Takahiro Hanyu; Masami Nakajima; Kazutami Arimoto (ISMVL, 2007)

Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry. - Akira Mochizuki; Hirokatsu Shirahama; Takahiro Hanyu (IEICE Trans. Electron., 2007)

Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. - Hirokatsu Shirahama; Takahiro Hanyu (ISMVL, 2008)

Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. - Takashi Matsuura; Hirokatsu Shirahama; Masanori Natsui; Takahiro Hanyu (ISMVL, 2009)

Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme. - Hirokatsu Shirahama; Takashi Matsuura; Masanori Natsui; Takahiro Hanyu (IEICE Trans. Inf. Syst., 2010)

Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link. - Akira Mochizuki; Hirokatsu Shirahama; Naoya Onizawa; Takahiro Hanyu (APCCAS, 2014)

Energy-aware current-mode inter-chip link for a dependable GALS NoC platform. - Hirokatsu Shirahama; Akira Mochizuki; Yuma Watanabe; Takahiro Hanyu (ISCAS, 2014)

Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link. - Akira Mochizuki; Hirokatsu Shirahama; Takahiro Hanyu (ISMVL, 2014)

Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip. - Akira Mochizuki; Hirokatsu Shirahama; Yuma Watanabe; Takahiro Hanyu (IEICE Trans. Inf. Syst., 2014)

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. - Naoya Onizawa; Akira Mochizuki; Hirokatsu Shirahama; Masashi Imai; Tomohiro Yoneda; Takahiro Hanyu (IEICE Trans. Inf. Syst., 2014)