A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory. - Satoshi Kaneko; Hiroyuki Kondo; Norio Masui; Koichi Ishimi; Teruyuki Itou; Masayuki Satou; Naoto Okumura; Yukari Takata; Hirokazu Takata; Mamoru Sakugawa; Takashi Higuchi; Sugako Ohtani; et al. (IEEE J. Solid State Circuits, 2004)

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors. - Hiroyuki Kondo; Masami Nakajima; Norio Masui; Sugako Otani; Naoto Okumura; Yukari Takata; Takashi Nasu; Hirokazu Takata; Takashi Higuchi; Mamoru Sakugawa; Hayato Fujiwara; Kazuya Ishida; et al. (IEEE J. Solid State Circuits, 2008)

Dynamic Projection Mapping on Multiple Non-rigid Moving Objects for Stage Performance Applications. - Ryohei Nakatsu; Ningfeng Yang; Hirokazu Takata; Takashi Nakanishi; Makoto Kitaguchi; Naoko Tosa (ICEC, 2018)

Clear Fundus Images Through High-Speed Tracking Using Glare-Free IR Color Technology. - Motoshi Sobue; Hirokazu Takata; Hironari Takehara; Makito Haruta; Hiroyuki Tashiro; Kiyotaka Sasagawa; Ryo Kawasaki; Jun Ohta (J. Robotics Mechatronics, 2022)