Edge-Based TACCS: A More Scalable TACCS Based on Cooperation of High Functional Edge Nodes. - Hiroki Date; Kenta Yasukawa; Ken-ichi Baba; Katsunori Yamaoka (CCNC, 2007)

Theoretical Analysis of Difference Between Edge-Based and Core-Node-Supported TACCS. - Hiroki Date; Kenta Yasukawa; Ken-ichi Baba; Katsunori Yamaoka (GLOBECOM, 2007)

An offload method for traffic distribution based on service identification. - Hiroki Date; Takashi Kurimoto; Akira Misawa (ICON, 2011)

Low-Offset, Low-Power Latched Comparator Using Capacitive Averaging Technique. - Kenichi Ohhata; Hiroki Date; Mai Arita (IEICE Trans. Electron., 2011)

Proposal of scale-out control architecture of virtual wide area layer-2 switch on metro network. - Hiroki Date; Kenichi Higuchi; Masaru Katayama; Akira Misawa (APCC, 2013)

Flow burst conversion for large-scale optical layer-2 switch network based on scale-out flow control method. - Kyota Hattori; Masahiro Nakagawa; Hiroki Date; Masaru Katayama; Hiroaki Ogawa (ECOC, 2014)

Evaluation of parallel processing control of virtual switch architecture on large-scale network. - Hiroki Date; Kenichi Higuchi; Masaru Katayama; Hiroaki Ogawa (GLOBECOM, 2014)

Scalable Centralized Control Architecture of Virtual Switch on Large-Scale Network. - Hiroki Date; Kenichi Higuchi; Masaru Katayama; Katsutoshi Koda (IEICE Trans. Commun., 2015)

Resolution of network topology using fast graph mining. - Shohei Kamamura; Aki Fukuda; Hiroshi Yamamoto; Hiroki Date; Rie Hayashi; Yoshihiko Uematsu (ICC, 2017)

Recommendation-Based Bandwidth Calendaring for Packet Transport Network. - Shohei Kamamura; Rie Hayashi; Hiroki Date; Hiroshi Yamamoto; Takashi Miyamura; Yoshihiko Uematsu; Kouichi Genda (IEICE Trans. Commun., 2017)

Future Nationwide Optical Network Architecture for Higher Availability and Operability Using Transport SDN Technologies. - Yoshihiko Uematsu; Shohei Kamamura; Hiroki Date; Hiroshi Yamamoto; Aki Fukuda; Rie Hayashi; Katsutoshi Koda (IEICE Trans. Commun., 2018)

A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology. - Noboru Shibata; Kazushige Kanda; Takahiro Shimizu; Jun Nakai; Osamu Nagao; Naoki Kobayashi 004; Makoto Miakashi; Yasushi Nagadomi; Takeshi Nakano; Takahisa Kawabe; Taira Shibuya; Mario Sako; et al. (ISSCC, 2019)

A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology. - Noboru Shibata; Takahisa Kawabe; Taira Shibuya; Mario Sako; Kosuke Yanagidaira; Toshifumi Hashimoto; Hiroki Date; Manabu Sato; Tomoki Nakagawa; Junji Musha; Takatoshi Minamoto; Kazushige Kanda; et al. (IEEE J. Solid State Circuits, 2020)

30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology. - Tsutomu Higuchi; Takuyo Kodama; Koji Kato; Ryo Fukuda; Naoya Tokiwa; Mitsuhiro Abe; Teruo Takagiwa; Yuki Shimizu; Junji Musha; Katsuaki Sakurai; Jumpei Sato; Tetsuaki Utsumi; et al. (ISSCC, 2021)

Soft-failure Identification and Localization Method Based on Received Optical Signal Quality and Repeater Nodes' Performance. - Hiroshi Yamamoto; Kouhei Watanabe; Hiroki Date; Daisaku Shimazaki; Yutaka Fukuchi; Hideki Maeda (OFC, 2023)

A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os. - Kosuke Yanagidaira; Mario Sako; Yasuhiro Hirashima; Junya Matsuno; Yumi Higashi; Yutaka Shimizu; Akihiro Imamoto; Kazuaki Kawaguchi; Koji Tabata; Takeshi Nakano; Yusuke Ochi; Hiroaki Hoshino; et al. (ISSCC, 2025)