A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter. - Toru Tanzawa; Hiroyuki Shibayama; Ryota Terauchi; Katsumi Hisano; Hiroki Ishikuro; Shouhei Kousai; Hiroyuki Kobayashi; Hideaki Majima; Toru Takayama; Kenichi Agawa; Masayuki Koizumi; Fumitoshi Hatori (CICC, 2004)

A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations. - Daisuke Miyashita; Hiroki Ishikuro; Shouhei Kousai; Hiroyuki Kobayashi; Hideaki Majima; Kenichi Agawa; Mototsugu Hamada (CICC, 2005)

A 1.2-V CMOS complex bandpass filter with a tunable center frequency. - Hideaki Majima; Hiroki Ishikuro; Kenichi Agawa; Mototsugu Hamada (ESSCIRC, 2005)

A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters. - Toru Tanzawa; Kenichi Agawa; Hiroyuki Shibayama; Ryota Terauchi; Katsumi Hisano; Hiroki Ishikuro; Shouhei Kousai; Hiroyuki Kobayashi; Hideaki Majima; Toru Takayama; Masayuki Koizumi; Fumitoshi Hatori (IEICE Trans. Electron., 2005)

Compact outside-rail circuit structure by single-cascode two-transistor topology. - Atit Tamtrakarn; Hiroki Ishikuro; Koichi Ishida; Takayasu Sakurai (CICC, 2006)

Wideband Inductive-coupling Interface for High-performance Portable System. - Hiroki Ishikuro; Noriyuki Miura; Tadahiro Kuroda (CICC, 2007)

A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB Transmitter. - Vishal V. Kulkarni; Muhammad Muqsith; Hiroki Ishikuro; Tadahiro Kuroda (CICC, 2007)

An Attachable Wireless Chip Access Interface for Arbitrary Data Rate Using Pulse-Based lnductive-Coupling through LSI Package. - Hiroki Ishikuro; Toshihiko Sugahara; Tadahiro Kuroda (ISSCC, 2007)

A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. - Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2007)

An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors. - Koichi Ishida; Atit Tamtrakarn; Hiroki Ishikuro; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2007)

An 11Gb/s Inductive-Coupling Link with Burst Transmission. - Noriyuki Miura; Yoshinori Kohama; Yasufumi Sugimori; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2008)

Constant Magnetic Field Scaling in Inductive-Coupling Data Link. - Daisuke Mizoguchi; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEICE Trans. Electron., 2008)

A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. - Noriyuki Miura; Hiroki Ishikuro; Kiichi Niitsu; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2008)

A wireless real-time on-chip bus trace system. - Shusuke Kawai; Takayuki Ikari; Yutaka Takikawa; Hiroki Ishikuro; Tadahiro Kuroda (ASP-DAC, 2009)

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. - Mitsuko Saito; Yasufumi Sugimori; Yoshinori Kohama; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (CICC, 2009)

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. - Yasufumi Sugimori; Yoshinori Kohama; Mitsuko Saito; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2009)

A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna. - Vishal V. Kulkarni; Muhammad Muqsith; Kiichi Niitsu; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2009)

A High-Speed Inductive-Coupling Link With Burst Transmission. - Noriyuki Miura; Yoshinori Kohama; Yasufumi Sugimori; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2009)

0.5 V multi-phase digital controlled oscillator with smooth phase transition circuit. - Abul Hasan Johari; Satoshi Kumaki; Takeshi Matsubara; Isamu Hayashi; Hiroki Ishikuro (APCCAS, 2010)

A 0.5V 6-bit scalable phase interpolator. - Satoshi Kumaki; Abul Hasan Johari; Takeshi Matsubara; Isamu Hayashi; Hiroki Ishikuro (APCCAS, 2010)

A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator. - Akira Shikata; Ryota Sekimoto; Hiroki Ishikuro (APCCAS, 2010)

A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card. - Shusuke Kawai; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2010)

Wireless proximity interfaces with a pulse-based inductive coupling technique. - Hiroki Ishikuro; Tadahiro Kuroda (IEEE Commun. Mag., 2010)

A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65 nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme. - Vishal V. Kulkarni; Hiroki Ishikuro; Tadahiro Kuroda (IEICE Trans. Electron., 2010)

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. - Mitsuko Saito; Yasufumi Sugimori; Yoshinori Kohama; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2010)

47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. - Mitsuko Saito; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. - Kiichi Niitsu; Yoshinori Kohama; Yasufumi Sugimori; Kazutaka Kasuga; Kenichi Osada; Naohiko Irie; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2010)

1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller. - Kazutoshi Tomita; Ryota Shinoda; Tadahiro Kuroda; Hiroki Ishikuro (A-SSCC, 2011)

A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface. - Won-Joo Yun; Hiroki Ishikuro; Tadahiro Kuroda (A-SSCC, 2011)

A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. - Ryota Sekimoto; Akira Shikata; Tadahiro Kuroda; Hiroki Ishikuro (ESSCIRC, 2011)

6W/25mm2 inductive power transfer for non-contact wafer-level testing. - Andrzej Radecki; Hayun Chung; Yoichi Yoshida; Noriyuki Miura; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2011)

A 12Gb/s non-contact interface with coupled transmission lines. - Tsutomu Takeya; Lan Nan; Shinya Nakano; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2011)

A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators. - Kiichi Niitsu; Vishwesh V. Kulkarni; Shinmo Kang; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. - Kiichi Niitsu; Yasufumi Sugimori; Yoshinori Kohama; Kenichi Osada; Naohiko Irie; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2011)

0.6 - 3.6 GHz wideband operation with high phase resolution On-Chip Network Analyzer. - Abul Hasan Johari; Hiroki Ishikuro (APCCAS, 2012)

A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers. - Atsutake Kosuge; Wataru Mizuhara; Noriyuki Miura; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (CICC, 2012)

A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOS. - Lechang Liu; Hiroki Ishikuro; Tadahiro Kuroda (CICC, 2012)

An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. - Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (ESSCIRC, 2012)

A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme. - Takayuki Abe; Yuxiang Yuan; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2012)

Voltage-boosting wireless power delivery system with fast load tracker by ΔΣ-modulated sub-harmonic resonant switching. - Ryota Shinoda; Kazutoshi Tomita; Yuya Hasegawa; Hiroki Ishikuro (ISSCC, 2012)

A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. - Won-Joo Yun; Shinya Nakano; Wataru Mizuhara; Atsutake Kosuge; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2012)

A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS. - Takeshi Matsubara; Isamu Hayashi; Abul Hasan Johari; Tadahiro Kuroda; Hiroki Ishikuro (RWS, 2012)

6 W/25 mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing. - Andrzej Radecki; Hayun Chung; Yoichi Yoshida; Noriyuki Miura; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda (IEICE Trans. Electron., 2012)

High-Frequency Precise Characterization of Intrinsic FinFET Channel. - Hideo Sakai; Shin-ichi O'Uchi; Takashi Matsukawa; Kazuhiko Endo; Yongxun Liu; Junichi Tsukada; Yuki Ishikawa; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike; Kunihiro Sakamoto; Meishoku Masahara; et al. (IEICE Trans. Electron., 2012)

A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS. - Hayun Chung; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2012)

A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards. - Hayun Chung; Andrzej Radecki; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2012)

Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication. - Andrzej Radecki; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2012)

Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card. - Andrzej Radecki; Yuxiang Yuan; Noriyuki Miura; Iori Aikawa; Yasuhiro Take; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2012)

A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS. - Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2012)

1-W 3.3-16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller. - Kazutoshi Tomita; Ryota Shinoda; Tadahiro Kuroda; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2012)

A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration. - Kiichi Niitsu; Shusuke Kawai; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. - Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (ASP-DAC, 2013)

A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. - Yuki Urano; Won-Joo Yun; Tadahiro Kuroda; Hiroki Ishikuro (ISCAS, 2013)

A voltage scaling 0.25-1.8 V delta-sigma modulator with inverter-opamp self-configuring amplifier. - Kentaro Yoshioka; Yosuke Toyama; Teruo Jyo; Hiroki Ishikuro (ISCAS, 2013)

A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. - Wataru Mizuhara; Tsunaaki Shidei; Atsutake Kosuge; Tsutomu Takeya; Noriyuki Miura; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2013)

3D clock distribution using vertically/horizontally-coupled resonators. - Yasuhiro Take; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2013)

A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA. - Teruo Jyo; Tadahiro Kuroda; Hiroki Ishikuro (RWS, 2013)

An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS. - Ryota Sekimoto; Akira Shikata; Kentaro Yoshioka; Tadahiro Kuroda; Hiroki Ishikuro (IEICE Trans. Electron., 2013)

A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller. - Akira Shikata; Ryota Sekimoto; Kentaro Yoshioka; Tadahiro Kuroda; Hiroki Ishikuro (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS. - Ryota Sekimoto; Akira Shikata; Kentaro Yoshioka; Tadahiro Kuroda; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2013)

A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. - Tsutomu Takeya; Lan Nan; Shinya Nakano; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2013)

An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. - Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (ASP-DAC, 2014)

A SAW-less LTE transmitter with high-linearity modulator using BPF-based I/Q summing. - Takahiro Nakamura; Naoki Kitazawa; Kaoru Kohira; Hiroki Ishikuro (ESSCIRC, 2014)

A 13b SAR ADC with eye-opening VCO based comparator. - Kentaro Yoshioka; Hiroki Ishikuro (ESSCIRC, 2014)

30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%. - Atsutake Kosuge; Shu Ishizuka; Lechang Liu; Akira Okada; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2014)

7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. - Kentaro Yoshioka; Ryo Saito; Takumi Danjo; Sanroku Tsukamoto; Hiroki Ishikuro (VLSIC, 2014)

A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. - Atsutake Kosuge; Wataru Mizuhara; Tsunaaki Shidei; Tsutomu Takeya; Noriyuki Miura; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2014)

Dual-output wireless power delivery system for small size large volume wireless memory card. - Junki Hashiba; Toru Kawajiri; Yuya Hasegawa; Hiroki Ishikuro (ASP-DAC, 2015)

A near-optimum 13.56 MHz active rectifier with circuit-delay real-time calibrations for high-current biomedical implants. - Cheng Huang 004; Toru Kawajiri; Hiroki Ishikuro (CICC, 2015)

A low EMI SIDO wireless power transfer system with 10μsec response time. - Toru Kawajiri; Takahiro Moroto; Hiroki Ishikuro (ESSCIRC, 2015)

A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration. - Koki Tanaka; Ryo Saito; Hiroki Ishikuro (ESSCIRC, 2015)

I/Q mismatch compensation ΔΣ modulator using ternary capacitor rotation technique. - Masaki Yonekura; Hiroki Ishikuro (ESSCIRC, 2015)

Fence loaded antenna coupler for high-band UWB with steep cutoff characteristics. - Isao Saito; Kaoru Kohira; Hiroki Ishikuro (RWS, 2015)

Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory. - Atsutake Kosuge; Junki Hashiba; Toru Kawajiri; So Hasegawa; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda; Ken Takeuchi (VLSIC, 2015)

Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC. - Kentaro Yoshioka; Ryo Saito; Takumi Danjo; Sanroku Tsukamoto; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2015)

Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers. - Atsutake Kosuge; Shu Ishizuka; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS. - Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Low power DT delta-sigma modulator with ring amplifier SC-integrator. - Takuma Suguro; Hiroki Ishikuro (ISCAS, 2016)

A programmable ΔΣ SAR-ADC with charge shuttling technique. - Kohei Yamada; Yosuke Toyama; Hiroki Ishikuro (ISOCC, 2016)

A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe. - Kaoru Kohira; Naoki Kitazawa; Hiroki Ishikuro (RWS, 2016)

A wireless power transfer system with enhanced response and efficiency by fully-integrated fast-tracking wireless constant-idle-time control for implants. - Cheng Huang 004; Toru Kawajiri; Hiroki Ishikuro (VLSI Circuits, 2016)

A 12.5Gbps CDR with Differential to Common Converting Edge Detector for the Wired and Wireless Serial Link. - Kaoru Kohira; Hiroki Ishikuro (IEICE Trans. Electron., 2016)

A 24 mW 5.7 Gbps Dual Frequency Conversion Demodulator for Impulse Radio with the First Sidelobe. - Kaoru Kohira; Naoki Kitazawa; Hiroki Ishikuro (IEICE Trans. Electron., 2016)

A Near-Optimum 13.56 MHz CMOS Active Rectifier With Circuit-Delay Real-Time Calibrations for High-Current Biomedical Implants. - Cheng Huang 004; Toru Kawajiri; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2016)

An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. - Atsutake Kosuge; Junki Hashiba; Toru Kawajiri; So Hasegawa; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda; Ken Takeuchi (IEEE J. Solid State Circuits, 2016)

A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver. - Atsutake Kosuge; Akira Okada; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Distortion and its suppression in low-power delta-sigma modulator. - Hiroki Ishikuro (MWSCAS, 2017)

Design of resource sharing reconfigurable ΔΣ SAR-ADC. - Motomi Ishizuka; Kohei Yamada; Hiroki Ishikuro (ASP-DAC, 2018)

A High-Resolution Time-Based Resistance-to-Digital Converter with TDC and Counter. - Shuya Nakagawa; Kaito Horikoshi; Hiroki Ishikuro (MWSCAS, 2018)

A 13.56-MHz Wireless Power Transfer System With Enhanced Load-Transient Response and Efficiency by Fully Integrated Wireless Constant-Idle-Time Control for Biomedical Implants. - Cheng Huang 004; Toru Kawajiri; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2018)

A High Accuracy Opamp-less Interface Circuit for 2-D Cross-Point Resistive Sensor Array with Switch Resistance Calibration. - Yohsuke Shiiki; Hiroki Ishikuro (APCCAS, 2019)

High-Resolution Auto-Balancing Wheatstone-Bridge with Successive Approximation of ΔΣ-Modulated Digitally Controlled Variable Resistor. - Takumi Miyazaki; Shuya Nakagawa; Hiroki Ishikuro (ICECS, 2019)

A Differential-Ring-Oscillator with up to 35 dBc/Hz Phase Noise Improving Amplitude Feedback Loop for Ultra Low Power Systems. - Peter Toth; Hiroki Ishikuro (ICECS, 2019)

Interface with Opamp Output-Impedance Calibration Technique for a Large Integrated 2-D Resistive Sensor Array. - Yohsuke Shiiki; Hiroki Ishikuro (ISCAS, 2019)

Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets. - Takahisa Tanaka; K. Tabuchi; Kohei Tatehora; Yohsuke Shiiki; S. Nakagawa; Tsunaki Takahashi; R. Shimizu; Hiroki Ishikuro; Tadahiro Kuroda; T. Yanagida; Ken Uchida (VLSI Circuits, 2019)

Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. - Kentaro Yoshioka; Tomohiko Sugimoto; Naoya Waki; Sinnyoung Kim; Daisuke Kurose; Hirotomo Ishii; Masanori Furuta; Akihide Sai; Hiroki Ishikuro; Tetsuro Itakura (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Highly Linear Amp-Less Interface Circuit for Capacitive Sensors with ΔΣ C-DAC. - Yuya Maekawa; Syuya Nakagawa; Hiroki Ishikuro (APCCAS, 2020)

A Linearity Testing of Cascaded Analog Mixed-Signal Blocks Using SEIR Method. - Tatsuya Ishikawa; Chia-Wei Pai; Hiroki Ishikuro (I2MTC, 2020)

A Digital-to-Resistance Converter with an Automatic Offset Calibration Method for Evaluating Dynamic Performance of Resistive Sensor Readout Circuits. - Shuya Nakagawa; Takumi Miyazaki; Hiroki Ishikuro (I2MTC, 2020)

A High-Resolution Oscillator Based Resistance-to-Digital Converter with Non-Linearity Canceling Feedback by ΔΣ Modulated Variable Resistor. - Shuya Nakagawa; Takumi Miyazaki; Hiroki Ishikuro (ISCAS, 2020)

A 0.12V Fully Integrated Charge Pump with Gate Voltage Optimization for Energy Harvesting Applications. - Yi Tan; Yohsuke Shiiki; Hiroki Ishikuro (ISCAS, 2020)

A Wide Range and High Accuracy Sensor Interface with Switching Regulator for Coin-Cell Powered Tiny Wireless Sensor Node. - Kohei Tatehora; Yohsuke Shiiki; S. Nakagawa; Takahisa Tanaka; Ken Uchida; Hiroki Ishikuro (ISCAS, 2020)

A Discrete-Time Model for Frequency Modulated Charge Pumps with Synchronized Controller. - Yi Tan; Hiroki Ishikuro (MWSCAS, 2020)

A Wide Input-Range, Low-Power and Highly Flexible 18 Bit Time-to-Digital Converter with Compact Differential Circuit Topology. - Peter Toth; Hiroki Ishikuro (MWSCAS, 2020)

Gate Voltage Optimization in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting. - Yi Tan; Yohsuke Shiiki; Hiroki Ishikuro (ASP-DAC, 2021)

An up to 35 dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems. - Peter Toth; Hiroki Ishikuro (ASP-DAC, 2021)

An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept. - Peter Toth; Hiroki Ishikuro (ASP-DAC, 2021)

A Switched-Capacitor DC-DC Converter with >77.3% Efficiency and 80 ns Active Transient Response in 40 µA - 4 mA Load Current Range. - Yi Tan; Hiroki Ishikuro (ESSCIRC, 2021)

An Amp-Less Time-Domain AC Bridge for Impedance Spectroscopy with 1-bit $ Delta Sigma$ DAC. - Yuya Maekawa; Hiroki Ishikuro (ICECS, 2021)

Robust Readout Circuit with Leakage Current Cancellation Technique for Stretchable Touch Sensors. - Kaoru Yamashita; Tokihiko Shimura; Shun Sato; Naoji Matsuhisa; Hiroki Ishikuro (ICECS, 2021)

A Fast Wake-Up and High Accuracy Sensor Interface by Synchronous Sampling with Power-Efficient Switching Regulator. - Yuya Fuketa; Kohei Tatehora; Yohsuke Shiiki; Shuya Nakagawa; Hiroki Ishikuro (MWSCAS, 2021)

Enhanced Drain Current in Transient Mode due to Long Ionization Time of Shallow Impurities at 4 K in 65-nm bulk Cryo CMOS Transistors. - Tomohisa Miyao; Takahisa Tanaka; Itsuki Imanishi; Masayuki Ichikawa; Shuya Nakagawa; Hiroki Ishikuro; Toshitsugu Sakamoto; Munehiro Tada; Ken Uchida (DRC, 2022)

A Dual-Mode 2: 1 Switched Capacitor Converter with >65% Efficiency over 1000x Load Current Range and One Clock Cycle Transient Response. - Yi Tan; Hiroki Ishikuro (ICECS 2022, 2022)

T/R Switch Composed of Three HV-MOSFETs With 12.1-μW Consumption That Enables Per-Channel Self-Loopback AC Tests and -18.1-dB Switching Noise Suppression for 3-D Ultrasound Imaging With 3072-Ch Transceiver. - Shinya Kajiyama; Yutaka Igarashi; Toru Yazaki; Yusaku Katsube; Takuma Nishimoto; Tatsuo Nakagawa; Yohei Nakamura; Yoshihiro Hayashi; Takuya Kaneko; Hiroki Ishikuro; Taizo Yamawaki (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Optimization of Gate Voltage in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting. - Yi Tan; Yohsuke Shiiki; Hiroki Ishikuro (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration. - Kaoru Yamashita; Benjamin P. Hershberg; Kentaro Yoshioka; Hiroki Ishikuro (CICC, 2023)

An Oscillator with Inductively Coupled Resonators for Readout of Stretchable Resistive Strain Sensor. - Billy Mårtensson; Hinata Mitomo; Baktash Behmanesh; Naoji Matsuhisa; Hiroki Ishikuro (MWSCAS, 2023)

A High-Speed Low-Power Two-Stage Comparator with Regeneration Enhancement and Through Current Suppression Techniques. - Chia-Wei Pai; Hiroki Ishikuro (MWSCAS, 2023)

An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs. - Shusuke Kawai; Takeshi Ueno; Hiroki Ishikuro; Kohei Onizuka (IEEE J. Solid State Circuits, 2023)

A Cryogenic 12 GHz Frequency Doubler With Temperature Compensation for Trapped-Ion Quantum Computer. - Peter Toth; Alexander Meyer; Sebastian Halama; Hiroki Ishikuro; Vadim Issakov (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Direct Digital Synthesizer-Based Arbitrary Waveform Generator for Envelope Modulation in Trapped-Ion Quantum Computer Operating at 4K. - Paul Shine Eugine; Peter Toth; Kaoru Yamashita; Sebastian Halama; Christian Ospelkaus; Hiroki Ishikuro; Vadim Issakov (BCICTS, 2024)

A 10-bit 100kS/s SAR ADC With a Monotonic Capacitor Switching Procedure for Single-Ended Inputs in 22nm CMOS FDSOI. - Alexander Meyer; Kaoru Yamashita; Adilet Dossanov; Martin Maier; Finn Stapelfeldt; Yerzhan Kudabay; Peter Toth; Fa Foster Dai; Hiroki Ishikuro; Vadim Issakov (ISCAS, 2024)

Orthogonal Decomposition Based Digital Controller Design for Hybrid Converter. - Yi Tan; Jianqiang Jiang; Cheng Huang 004; Hiroki Ishikuro (MWSCAS, 2024)

A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator. - Chia-Wei Pai; Ken Uchida; Munehiro Tada; Hiroki Ishikuro (Microelectron. J., 2024)

Design and analysis of a high-speed low-power comparator with regeneration enhancement and through current suppression techniques from 4 K to 300 K in 65-nm Cryo-CMOS. - Chia-Wei Pai; Ken Uchida; Munehiro Tada; Hiroki Ishikuro (Microelectron. J., 2024)

A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration. - Kaoru Yamashita; Benjamin P. Hershberg; Kentaro Yoshioka; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2024)

Design of Dual Lower Bound Hysteresis Control in Switched-Capacitor DC-DC Converter for Optimum Efficiency and Transient Speed in Wide Loading Range for IoT Application. - Yi Tan; Cheng Huang 004; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2024)

A 4.6-373K Functional 800MS/s 12b Buffer-then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC with Integrated-Active-Hold Technique. - Kaoru Yamashita; Kentaro Yoshioka; Christian Ziegler; Vadim Issakov; Hiroki Ishikuro (CICC, 2025)

13.3 A Cryo-BiCMOS Controller for 9Be+-Trapped-Ion-Based Quantum Computers. - Peter Toth; Paul Shine Eugine; Sebastian Halama; Yerzhan Kudabay; Kaoru Yamashita; Hiroki Ishikuro; Christian Ospelkaus; Vadim Issakov (ISSCC, 2025)