A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier. - Katsunori Seno; Kurt Knorpp; Lee-Lean Shu; Naoki Teshima; Hiroki Kihara; Hiroshi Sato; Fumio Miyaji; Minoru Takeda; Masayoshi Sasaki; Yoichi Tomo; Patrick T. Chuang; Kazuyoshi Kobayashi (IEEE J. Solid State Circuits, 1993)

A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator. - Kenichi Maruko; Tatsuya Sugioka; Hiroaki Hayashi; Zhiwei Zhou; Yasunori Tsukuda; Yuki Yagishita; Hironobu Konishi; Toshikyuki Ogata; Hisashi Owa; Taichi Niki; Kenji Konda; Masahiro Sato; et al. (ISSCC, 2010)