A BIST scheme using microprogram ROM for large capacity memories. - Hiroki Koike; Toshio Takeshima; Masahide Takada (ITC, 1990)

A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM. - Toshio Takeshima; Masahide Takada; Hiroki Koike; Hiroshi Watanabe; Shigeru Koshimaru; Kenjiro Mitake; Wataru Kikuchi; Takaho Tanigawa; Tatsunori Murotani; Kenji Noda; Kazuhiro Tasaka; Koji Yamanaka; et al. (IEEE J. Solid State Circuits, 1990)

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. - Akira Tanabe; Toshio Takeshima; Hiroki Koike; Yoshiharu Aimoto; Masahide Takada; Toshiyuki Ishijima; Naoki Kasai; Hiromitsu Hada; Kentaro Shibahara; Takemitsu Kunio; Takaho Tanigawa; Takanori Saeki; et al. (IEEE J. Solid State Circuits, 1992)

An embedded FeRAM macro cell for a smart card microcontroller. - Tohru Miwa; Junichi Yamada; Yuji Okamoto; Hiroki Koike; Hideo Toyoshiina; Hiromitsu Hada; Yoshihiro Hayashi; Hiroaki Oliizaki; Yoichi Miyasalca; Takemitsu Kunio; Hidenobu Miyamoto; Hideki Gomi; et al. (CICC, 1998)

NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors. - Tohm Miwa; Junichi Yamada; Hiroki Koike; Hideo Toyoshima; Kazushi Amanuma; Sota Kobayashi; Tom Tatsumi; Yukihiro Maejima; Hiromitsu Hada; Takemitsu Kunio (CICC, 2000)

FeRAM device and circuit technologies fully compatible with advanced CMOS. - Hideo Toyoshima; Sota Kobayashi; Junichi Yamada; Tohru Miwa; Hiroki Koike; Hidenori Takeuchi; Hidemitsu Mori; Naoki Kasai; Yukihiko Maejima; Nobuhira Tanabe; Toru Tatsumi; Hiromitsu Hada (CICC, 2001)

NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors. - Tohru Miwa; Junichi Yamada; Hiroki Koike; Hideo Toyoshima; Kazushi Amanuma; Sota Kobayashi; Toru Tatsumi; Yukihiko Maejima; Hiromitsu Hada; Takemitsu Kunio (IEEE J. Solid State Circuits, 2001)

A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers. - Junichi Yamada; Tohru Miwa; Hiroki Koike; Hideo Toyoshima; Kazushi Amanuma; Sota Kobayashi; Toru Tatsumi; Yukihiko Maejima; Hiromitsu Hada; Hidemitsu Mori; Seiichi Takahashi; Hidenori Takeuchi; et al. (IEEE J. Solid State Circuits, 2002)

An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function. - Hiroyuki Morimoto; Hiroki Koike; Kazuyuki Nakamura (ASP-DAC, 2010)

An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O. - Hiroyuki Morimoto; Hiroki Koike; Kazuyuki Nakamura (IEICE Trans. Electron., 2011)

High-speed simulator including accurate MTJ models for spintronics integrated circuit design. - Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Hiroaki Honjo; Tadahiko Sugibayashi; Hiroki Koike; Takashi Ohsawa; Shunsuke Fukami; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (ISCAS, 2012)

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. - Takashi Ohsawa; Hiroki Koike; Sadahiko Miura; Hiroaki Honjo; Keiichi Tokutome; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (VLSIC, 2012)

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. - Takashi Ohsawa; Hiroki Koike; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (IEEE J. Solid State Circuits, 2013)

Isomorphic tetravalent cyclic Haar graphs. - Hiroki Koike; István Kovács (Ars Math. Contemp., 2014)

Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. - Masanori Natsui; Akira Tamakoshi; Akira Mochizuki; Hiroki Koike; Hideo Ohno; Tetsuo Endoh; Takahiro Hanyu (ISCAS, 2016)

An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. - Tetsuo Endoh; Hiroki Koike; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. - Takahiro Hanyu; Tetsuo Endoh; Daisuke Suzuki; Hiroki Koike; Yitao Ma; Naoya Onizawa; Masanori Natsui; Shoji Ikeda; Hideo Ohno (Proc. IEEE, 2016)

Flag Bicolorings, Pseudo-Orientations, and Double Covers of Maps. - Hiroki Koike; Daniel Pellicer; Miguel Raggi; Steve Wilson 001 (Electron. J. Comb., 2017)

Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system. - Ryo Tamura; I. Mori; N. Watanabe; Hiroki Koike; Tetsuo Endoh (NVMTS, 2018)

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (ISSCC, 2019)

A novel memory test system with an electromagnet for STT-MRAM testing. - Ryo Tamura; N. Watanabe; Hiroki Koike; Hideo Sato; Shoji Ikeda; Tetsuo Endoh; Soshi Sato (NVMTS, 2019)

Cyclic groups are CI-groups for balanced configurations. - Hiroki Koike; István Kovács; Dragan Marusic; Mikhail E. Muzychuk (Des. Codes Cryptogr., 2019)

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (IEEE J. Solid State Circuits, 2019)

Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability. - K. Watanabe; T. Shimada; K. Hirose; H. Shindo; D. Kobayashi; Takaho Tanigawa; Shoji Ikeda; Takamitsu Shinada; Hiroki Koike; Tetsuo Endoh; T. Makino; Takeshi Ohshima (IRPS, 2022)