An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. - Yohei Hasegawa; Shohei Abe; Hiroki Matsutani; Hideharu Amano; Kenichiro Anjo; Toru Awashima (FPT, 2005)

Mobile Gateways for Mobile Ad-Hoc Networks with Network Mobility Support. - Ryuji Wakikawa; Hiroki Matsutani; Rajeev Koodli; Anders Nilsson 003; Jun Murai (ICN (2), 2005)

Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. - Hiroki Matsutani; Michihiro Koibuchi; Yutaka Yamada; Akiya Jouraku; Hideharu Amano (ICPP Workshops, 2005)

Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (PDPTA, 2005)

A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (PDCS, 2006)

A Parametric Study of Scalable Interconnects on FPGAs. - Daihan Wang; Hiroki Matsutani; Masato Yoshimi; Michihiro Koibuchi; Hideharu Amano (ERSA, 2006)

Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ISPA, 2006)

A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. - Daihan Wang; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (FPL, 2007)

Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ICPP, 2007)

Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IPDPS, 2007)

A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. - Daihan Wang; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2007)

Run-time power gating of on-chip routers using look-ahead routing. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Daihan Wang (ASP-DAC, 2008)

A link removal methodology for Networks-on-Chip on reconfigurable systems. - Daihan Wang; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (FPL, 2008)

Three-Dimensional Layout of On-Chip Tree-Based Networks. - Hiroki Matsutani; Michihiro Koibuchi; D. Frank Hsu; Hideharu Amano (ISPAN, 2008)

A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. - Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano; Timothy Mark Pinkston (NOCS, 2008)

Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. - Hiroki Matsutani; Michihiro Koibuchi; Daihan Wang; Hideharu Amano (NOCS, 2008)

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. - Shotaro Saito; Yoshinori Kohama; Yasufumi Sugimori; Yohei Hasegawa; Hiroki Matsutani; Toru Sano; Kazutaka Kasuga; Yoichi Yoshida; Kiichi Niitsu; Noriyuki Miura; Tadahiro Kuroda; Hideharu Amano (FPL, 2009)

Prediction router: Yet another low latency on-chip router architecture. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tsutomu Yoshinaga (HPCA, 2009)

Balanced Dimension-Order Routing for k-ary n-cubes. - José Miguel Montañana Aliaga; Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano (ICPP Workshops, 2009)

An on/off link activation method for low-power ethernet in PC clusters. - Michihiro Koibuchi; Tomohiro Otsuka; Hiroki Matsutani; Hideharu Amano (IPDPS, 2009)

Evaluation of a multicore reconfigurable architecture with variable core sizes. - Vu Manh Tuan; Naohiro Katsura; Hiroki Matsutani; Hideharu Amano (IPDPS, 2009)

An On/Off Link Activation Method for Power Regulation in InfiniBand. - José Miguel Montañana Aliaga; Michihiro Koibuchi; Takafumi Watanabe; Tomoyuki Hiroyasu; Hiroki Matsutani; Hideharu Amano (PDPTA, 2009)

A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs. - Daihan Wang; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2009)

Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. - Hiroki Matsutani; Michihiro Koibuchi; Yutaka Yamada; D. Frank Hsu; Hideharu Amano (IEEE Trans. Parallel Distributed Syst., 2009)

An Efficient Path Setup for a Photonic Network-on-Chip. - Cisse Ahmadou Dit Adi; Hiroki Matsutani; Michihiro Koibuchi; Hidetsugu Irie; Takefumi Miyoshi; Tsutomu Yoshinaga (ICNC, 2010)

A variable-pipeline on-chip router optimized to traffic pattern. - Yuto Hirata; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (NoCArc@MICRO, 2010)

Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. - José Miguel Montañana Aliaga; Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano (NAS, 2010)

A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. - Yuri Nishikawa; Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano (NAS, 2010)

Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. - Hiroki Matsutani; Michihiro Koibuchi; Daisuke Ikebuchi; Kimiyoshi Usami; Hiroshi Nakamura; Hideharu Amano (NOCS, 2010)

Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. - Hiroki Matsutani; Michihiro Koibuchi; Hiroshi Nakamura; Hideharu Amano (Low Power Networks-on-Chip, 2011)

Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects. - Michihiro Koibuchi; Takafumi Watanabe; Atsushi Minamihata; Masahiro Nakao; Tomoyuki Hiroyasu; Hiroki Matsutani; Hideharu Amano (ICNC, 2011)

A vertical bubble flow network using inductive-coupling for 3-D CMPs. - Hiroki Matsutani; Yasuhiro Take; Daisuke Sasaki; Masayuki Kimura; Yuki Ono; Yukinori Nishiyama; Michihiro Koibuchi; Tadahiro Kuroda; Hideharu Amano (NOCS, 2011)

Dynamic Voltage and Frequency Scaling for Real-Time Scheduling on a Prioritized SMT Processor. - Kei Fujii; Hiroyuki Chishiro; Hiroki Matsutani; Nobuyuki Yamasaki (RTCSA (2), 2011)

Design and Implementation of On-Chip Adaptive Router with Predictor for Regional Congestion. - Masakazu Taniguchi; Hiroki Matsutani; Nobuyuki Yamasaki (RTCSA (2), 2011)

A Dynamic Link-Width Optimization for Network-on-Chip. - Daihan Wang; Michihiro Koibuchi; Tomohiro Yoneda; Hiroki Matsutani; Hideharu Amano (RTCSA (2), 2011)

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. - Cisse Ahmadou Dit Adi; Hiroki Matsutani; Michihiro Koibuchi; Hidetsugu Irie; Takefumi Miyoshi; Tsutomu Yoshinaga (Int. J. Netw. Comput., 2011)

Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tsutomu Yoshinaga (IEEE Trans. Computers, 2011)

Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. - Hiroki Matsutani; Michihiro Koibuchi; Daisuke Ikebuchi; Kimiyoshi Usami; Hiroshi Nakamura; Hideharu Amano (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

3-D NoC on Inductive Wireless Interconnect. - Hiroki Matsutani; Michihiro Koibuchi; Tadahiro Kuroda; Hideharu Amano (3D Integration for NoC-based SoC Architectures, 2011)

Vertical Link On/Off Control Methods for Wireless 3-D NoCs. - Hao Zhang 020; Hiroki Matsutani; Yasuhiro Take; Tadahiro Kuroda; Hideharu Amano (ARCS, 2012)

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. - Hiroki Matsutani; Yuto Hirata; Michihiro Koibuchi; Kimiyoshi Usami; Hiroshi Nakamura; Hideharu Amano (ASP-DAC, 2012)

Dependable Responsive Multithreaded Processor for distributed real-time systems. - Kazutoshi Suito; Kei Fujii; Hiroki Matsutani; Nobuyuki Yamasaki (COOL Chips, 2012)

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. - Yusuke Koizumi; Eiichi Sasaki; Hideharu Amano; Hiroki Matsutani; Yasuhiro Take; Tadahiro Kuroda; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPL, 2012)

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. - Yusuke Koizumi; Hideharu Amano; Hiroki Matsutani; Noriyuki Miura; Tadahiro Kuroda; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPT, 2012)

A case for random shortcut topologies for HPC interconnects. - Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano; D. Frank Hsu; Henri Casanova (ISCA, 2012)

Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router. - Takeo Nakamura; Hiroki Matsutani; Michihiro Koibuchi; Kimiyoshi Usami; Hideharu Amano (MCSoC, 2012)

Adaptive Data Compression on 3D Network-on-Chips. - Yuan He 002; Hiroki Matsutani; Hiroshi Sasaki 001; Hiroshi Nakamura (Inf. Media Technol., 2012)

The Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems. - Kazutoshi Suito; Rikuhei Ueda; Kei Fujii; Takuma Kogo; Hiroki Matsutani; Nobuyuki Yamasaki (IEEE Micro, 2012)

A case for wireless 3D NoCs for CMPs. - Hiroki Matsutani; Paul Bogdan; Radu Marculescu; Yasuhiro Take; Daisuke Sasaki; Hao Zhang 020; Michihiro Koibuchi; Tadahiro Kuroda; Hideharu Amano (ASP-DAC, 2013)

Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links. - Hao Zhang 020; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (COOL Chips, 2013)

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. - Yusuke Koizumi; Noriyuki Miura; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPL, 2013)

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. - Noriyuki Miura; Yusuke Koizumi; Eiichi Sasaki; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (Hot Chips Symposium, 2013)

Layout-conscious random topologies for HPC off-chip interconnects. - Michihiro Koibuchi; Ikki Fujiwara; Hiroki Matsutani; Henri Casanova (HPCA, 2013)

Research Challenges on 2-D and 3-D Network-on-Chips. - Hiroki Matsutani (CANDAR, 2013)

A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity. - Daisuke Sasaki; Hao Zhang 020; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ICA3PP (2), 2013)

Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture. - Takahiro Kagami; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (NOCS, 2013)

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs. - Hao Zhang 020; Hiroki Matsutani; Yasuhiro Take; Tadahiro Kuroda; Hideharu Amano (IEICE Trans. Inf. Syst., 2013)

A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. - Noriyuki Miura; Yusuke Koizumi; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (IEEE Micro, 2013)

Low-latency wireless 3D NoCs via randomized shortcut chips. - Hiroki Matsutani; Michihiro Koibuchi; Ikki Fujiwara; Takahiro Kagami; Yasuhiro Take; Tadahiro Kuroda; Paul Bogdan; Radu Marculescu; Hideharu Amano (DATE, 2014)

Skywalk: A Topology for HPC Networks with Low-Delay Switches. - Ikki Fujiwara; Michihiro Koibuchi; Hiroki Matsutani; Henri Casanova (IPDPS, 2014)

Introduction to the special session on "Interconnect enhances architecture: Evolution of wireless NoC from planar to 3D". - Radu Marculescu; Partha Pratim Pande; Deuk Hyoun Heo; Hiroki Matsutani (NOCS, 2014)

Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs. - Hao Zhang 020; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

Performance Evaluations of Graph Database using CUDA and OpenMP Compatible Libraries. - Shin Morishima; Hiroki Matsutani (SIGARCH Comput. Archit. News, 2014)

3D NoC with Inductive-Coupling Links for Building-Block SiPs. - Yasuhiro Take; Hiroki Matsutani; Daisuke Sasaki; Michihiro Koibuchi; Tadahiro Kuroda; Hideharu Amano (IEEE Trans. Computers, 2014)

A metamorphotic Network-on-Chip for various types of parallel applications. - Seiichi Tade; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (ASAP, 2015)

Augmenting low-latency HPC network with free-space optical links. - Ikki Fujiwara; Michihiro Koibuchi; Tomoya Ozaki; Hiroki Matsutani; Henri Casanova (HPCA, 2015)

Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. - Hiroshi Nakahara; Tomoya Ozaki; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (MCSoC, 2015)

3D Shared Bus Architecture Using Inductive Coupling Interconnect. - Akio Nomura; Yu Fujita; Hiroki Matsutani; Hideharu Amano (MCSoC, 2015)

On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. - Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tadao Nakamura (NOCS, 2015)

Optimized Core-Links for Low-Latency NoCs. - Ryuta Kawano; Seiichi Tade; Ikki Fujiwara; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (PDP, 2015)

Performance Evaluations of Document-Oriented Databases Using GPU and Cache Structure. - Shin Morishima; Hiroki Matsutani (TrustCom/BigDataSE/ISPA (3), 2015)

A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface. - Ami Hayashi; Yuta Tokusashi; Hiroki Matsutani (SIGARCH Comput. Archit. News, 2015)

Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects. - Ikki Fujiwara; Michihiro Koibuchi; Hiroki Matsutani; Henri Casanova (IEEE Trans. Parallel Distributed Syst., 2015)

ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free. - Ryuta Kawano; Hiroshi Nakahara; Seiichi Tade; Ikki Fujiwara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ICIS, 2016)

An FPGA-based low-latency network processing for spark streaming. - Kohei Nakamura; Ami Hayashi; Hiroki Matsutani (IEEE BigData, 2016)

Distributed In-GPU Data Cache for Document-Oriented Data Store via PCIe over 10 Gbit Ethernet. - Shin Morishima; Hiroki Matsutani (Euro-Par Workshops, 2016)

NOSQL hardware appliance with multiple data structure. - Yuta Tokusashi; Hiroki Matsutani (Hot Chips Symposium, 2016)

A Multilevel NOSQL Cache Design Combining In-NIC and In-Kernel Caches. - Yuta Tokusashi; Hiroki Matsutani (Hot Interconnects, 2016)

LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies. - Ryuta Kawano; Hiroshi Nakahara; Ikki Fujiwara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (CANDAR, 2016)

Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface. - Akio Nomura; Hiroki Matsutani; Tadahiro Kuroda; Junichiro Kadomoto; Yusuke Matsushita 001; Hideharu Amano (CANDAR, 2016)

Accelerating Spark RDD Operations with Local and Remote GPU Devices. - Yasuhiro Ohno; Shin Morishima; Hiroki Matsutani (ICPADS, 2016)

Randomly Optimized Grid Graph for Low-Latency Interconnection Networks. - Koji Nakano; Daisuke Takafuji; Satoshi Fujita; Hiroki Matsutani; Ikki Fujiwara; Michihiro Koibuchi (ICPP, 2016)

Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. - Daichi Fujiki; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (PDP, 2016)

Design and implementation of hardware cache mechanism and NIC for column-oriented databases. - Akihiko Hamada; Hiroki Matsutani (ReConFig, 2016)

The Future of NoCs: New Technologies and Architectures. - Partha Pratim Pande; Sudeep Pasricha; Hiroki Matsutani (VLSID, 2016)

Optical network technologies for HPC: computer-architects point of view. - Michihiro Koibuchi; Ikki Fujiwara; Kiyo Ishii; Shu Namiki; Fabien Chaix; Hiroki Matsutani; Hideharu Amano; Tomohiro Kudoh (IEICE Electron. Express, 2016)

Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems. - Akram Ben Ahmed; Hiroki Matsutani; Michihiro Koibuchi; Kimiyoshi Usami; Hideharu Amano (IEICE Trans. Electron., 2016)

Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface. - Hiroshi Nakahara; Tomoya Ozaki; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2016)

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. - Takahiro Kagami; Hiroki Matsutani; Michihiro Koibuchi; Yasuhiro Take; Tadahiro Kuroda; Hideharu Amano (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Case for Uni-directional Network Topologies in Large-Scale Clusters. - Michihiro Koibuchi; Tomohiro Totoki; Hiroki Matsutani; Hideharu Amano; Fabien Chaix; Ikki Fujiwara; Henri Casanova (CLUSTER, 2017)

In-switch approximate processing: Delayed tasks management for MapReduce applications. - Koya Mitsuzuka; Ami Hayashi; Michihiro Koibuchi; Hideharu Amano; Hiroki Matsutani (FPL, 2017)

A Case for Remote GPUs over 10GbE Network for VR Applications. - Shin Morishima; Masahiro Okazaki; Hiroki Matsutani (HEART, 2017)

An FPGA NIC Based Hardware Caching for Blockchain. - Yuma Sakakibara; Kohei Nakamura; Hiroki Matsutani (HEART, 2017)

High-Bandwidth Low-Latency Approximate Interconnection Networks. - Daichi Fujiki; Kiyo Ishii; Ikki Fujiwara; Hiroki Matsutani; Hideharu Amano; Henri Casanova; Michihiro Koibuchi (HPCA, 2017)

Towards Tightly-coupled Datacenter with Free-space Optical Links. - Yao Hu; Hiroaki Hara; Ikki Fujiwara; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (ICCBDC, 2017)

HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ICPADS, 2017)

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. - Ryota Yasudo; Michihiro Koibuchi; Koji Nakano; Hiroki Matsutani; Hideharu Amano (ICPP, 2017)

Building block multi-chip systems using inductive coupling through chip interface. - Hideharu Amano; Tadahiro Kuroda; Hiroshi Nakamura; Kimiyoshi Usami; Masaaki Kondo; Hiroki Matsutani; Mitaro Namiki (ISOCC, 2017)

3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface. - Hiroshi Nakahara; Ryota Yasudo; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (ISPAN-FCST-ISCC, 2017)

An FPGA-based In-NIC Cache Approach for Lazy Learning Outlier Filtering. - Ami Hayashi; Hiroki Matsutani (PDP, 2017)

A Layout-Oriented Routing Method for Low-Latency HPC Networks. - Ryuta Kawano; Hiroshi Nakahara; Ikki Fujiwara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2017)

A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. - Ryuta Kawano; Hiroshi Nakahara; Seiichi Tade; Ikki Fujiwara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2017)

High-Performance with an In-GPU Graph Database Cache. - Shin Morishima; Hiroki Matsutani (IT Prof., 2017)

Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches. - Yuta Tokusashi; Hiroki Matsutani (IEEE Micro, 2017)

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. - Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tadao Nakamura (IEEE Trans. Computers, 2017)

Accelerating Online Change-Point Detection Algorithm Using 10 GbE FPGA NIC. - Takuma Iwata; Kohei Nakamura; Yuta Tokusashi; Hiroki Matsutani (Euro-Par Workshops, 2018)

OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector. - Mineto Tsukada; Masaaki Kondo; Hiroki Matsutani (Euro-Par Workshops, 2018)

MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel Memories. - Koya Mitsuzuka; Yuta Tokusashi; Hiroki Matsutani (FPT, 2018)

k-Optimized Path Routing for High-Throughput Data Center Networks. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Hideharu Amano (CANDAR, 2018)

An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization. - Naoya Niwa; Tomohiro Totoki; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (CANDAR Workshops, 2018)

Acceleration of Anomaly Detection in Blockchain Using In-GPU Cache. - Shin Morishima; Hiroki Matsutani (ISPA/IUCC/BDCloud/SocialCom/SustainCom, 2018)

Network Optimizations on Prediction Server with Multiple Predictors. - Kaho Okuyama; Yuta Tokusashi; Takuma Iwata; Mineto Tsukada; Kazumasa Kishiki; Hiroki Matsutani (ISPA/IUCC/BDCloud/SocialCom/SustainCom, 2018)

Accelerating Blockchain Transfer System Using FPGA-Based NIC. - Yuma Sakakibara; Yuta Tokusashi; Shin Morishima; Hiroki Matsutani (ISPA/IUCC/BDCloud/SocialCom/SustainCom, 2018)

Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. - Akram Ben Ahmed; Hayate Okuhara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (MCSoC, 2018)

Low-Reliable Low-Latency Networks Optimized for HPC Parallel Applications. - Truong Thao Nguyen; Hiroki Matsutani; Michihiro Koibuchi (NCA, 2018)

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. - Akram Ben Ahmed; Daichi Fujiki; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (NOCS, 2018)

Accelerating Blockchain Search of Full Nodes Using GPUs. - Shin Morishima; Hiroki Matsutani (PDP, 2018)

LaKe: The Power of In-Network Computing. - Yuta Tokusashi; Hiroki Matsutani; Noa Zilberman (ReConFig, 2018)

Special session on bringing cores closer together: The wireless revolution in on-chip communication. - Terrence S. T. Mak; Hiroki Matsutani; Partha Pratim Pande (VTS, 2018)

LaKe: An Energy Efficient, Low Latency, Accelerated Key-Value Store. - Yuta Tokusashi; Hiroki Matsutani; Noa Zilberman (CoRR, 2018)

Proxy Responses by FPGA-Based Switch for MapReduce Stragglers. - Koya Mitsuzuka; Michihiro Koibuchi; Hideharu Amano; Hiroki Matsutani (IEICE Trans. Inf. Syst., 2018)

A Hardware-Based Caching System on FPGA NIC for Blockchain. - Yuma Sakakibara; Shin Morishima; Kohei Nakamura; Hiroki Matsutani (IEICE Trans. Inf. Syst., 2018)

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. - Akio Nomura; Yusuke Matsushita 001; Junichiro Kadomoto; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano (Int. J. Netw. Comput., 2018)

Performance and Cost Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core. - Tomoya Itsubo; Mineto Tsukada; Hiroki Matsutani (COOL CHIPS, 2019)

Key-value Store Chip Design for Low Power Consumption. - Yuta Tokusashi; Hiroki Matsutani; Hideharu Amano (COOL CHIPS, 2019)

An Adaptive Abnormal Behavior Detection using Online Sequential Learning. - Rei Ito; Mineto Tsukada; Masaaki Kondo; Hiroki Matsutani (CSE/EUC, 2019)

Sparse 3-D NoCs with Inductive Coupling. - Michihiro Koibuchi; Lambert T. Leong; Tomohiro Totoki; Naoya Niwa; Hiroki Matsutani; Hideharu Amano; Henri Casanova (DAC, 2019)

Deadlock-Free Layered Routing for Infiniband Networks. - Ryuta Kawano; Hiroki Matsutani; Hideharu Amano (CANDAR Workshops, 2019)

An FPGA-Based Change-Point Detection for 10Gbps Packet Stream. - Takuma Iwata; Kohei Nakamura; Yuta Tokusashi; Hiroki Matsutani (IEICE Trans. Inf. Syst., 2019)

Designing High-Performance Interconnection Networks with Host-Switch Graphs. - Ryota Yasudo; Michihiro Koibuchi; Koji Nakano; Hiroki Matsutani; Hideharu Amano (IEEE Trans. Parallel Distributed Syst., 2019)

An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly Detection. - Takuya Sakuma; Hiroki Matsutani (COOL CHIPS, 2020)

An Edge Attribute-Wise Partitioning and Distributed Processing of R-GCN Using GPUs. - Tokio Kibata; Mineto Tsukada; Hiroki Matsutani (Euro-Par Workshops, 2020)

Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks. - Ryuta Kawano; Hiroki Matsutani; Hideharu Amano (CANDAR (Workshops), 2020)

A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection. - Yang Qin; Hiroki Matsutani; Masaaki Kondo (iThings/GreenCom/CPSCom/SmartData/Cybermatics, 2020)

Fast Semi-Supervised Anomaly Detection of Drivers' Behavior using Online Sequential Extreme Learning Machine. - Hiroki Oikawa; Tomoya Nishida; Ryuichi Sakamoto; Hiroki Matsutani; Masaaki Kondo (ITSC, 2020)

Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. - Tomoya Itsubo; Michihiro Koibuchi; Hideharu Amano; Hiroki Matsutani (PDP, 2020)

An On-Device Federated Learning Approach for Cooperative Anomaly Detection. - Rei Ito; Mineto Tsukada; Hiroki Matsutani (CoRR, 2020)

A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2020)

Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2020)

In-GPU Cache for Acceleration of Anomaly Detection in Blockchain. - Shin Morishima; Hiroki Matsutani (IEICE Trans. Inf. Syst., 2020)

A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices. - Mineto Tsukada; Masaaki Kondo; Hiroki Matsutani (IEEE Trans. Computers, 2020)

GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. - Ryuta Kawano; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ACIT, 2021)

A unified accelerator design for LiDAR SLAM algorithms for low-end FPGAs. - Keisuke Sugiura; Hiroki Matsutani (FPT, 2021)

Accelerating ODE-Based Neural Networks on Low-Cost FPGAs. - Hirohisa Watanabe; Hiroki Matsutani (IPDPS Workshops, 2021)

An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning. - Hirohisa Watanabe; Mineto Tsukada; Hiroki Matsutani (IPDPS Workshops, 2021)

Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. - Yoshiya Shikama; Ryuta Kawano; Hiroki Matsutani; Hideharu Amano; Yusuke Nagasaka; Naoto Fukumoto; Michihiro Koibuchi (PDP, 2021)

An On-Device Federated Learning Approach for Cooperative Model Update Between Edge Devices. - Rei Ito; Mineto Tsukada; Hiroki Matsutani (IEEE Access, 2021)

Particle Filter-based vs. Graph-based: SLAM Acceleration on Low-end FPGAs. - Keisuke Sugiura; Hiroki Matsutani (CoRR, 2021)

A DPDK-Based Acceleration Method for Experience Sampling of Distributed Reinforcement Learning. - Masaki Furukawa; Hiroki Matsutani (CoRR, 2021)

An Area-Efficient Recurrent Neural Network Core for Unsupervised Time-Series Anomaly Detection. - Takuya Sakuma; Hiroki Matsutani (IEICE Trans. Electron., 2021)

An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs. - Tomoya Itsubo; Michihiro Koibuchi; Hideharu Amano; Hiroki Matsutani (IEICE Trans. Inf. Syst., 2021)

An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm. - Keisuke Sugiura; Hiroki Matsutani (IEICE Trans. Inf. Syst., 2021)

An In-Network Parameter Aggregation using DPDK for Multi-GPU Deep Learning. - Masaki Furukawa; Tomoya Itsubo; Hiroki Matsutani (Int. J. Netw. Comput., 2021)

P3Net: PointNet-based Path Planning on FPGA. - Keisuke Sugiura; Hiroki Matsutani (FPT, 2022)

ONLAD-IDS: ONLAD-Based Intrusion Detection System Using SmartNIC. - Man Wu; Hiroki Matsutani; Masaaki Kondo (HPCC/DSS/SmartCity/DependSys, 2022)

Communication Size Reduction of Federated Learning based on Neural ODE Model. - Yuto Hoshino; Hiroki Kawakami; Hiroki Matsutani (CANDARW, 2022)

Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. - Ryuta Kawano; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (CANDAR, 2022)

A Packet Routing using Lightweight Reinforcement Learning Based on Online Sequential Learning. - Kenji Nemoto; Hiroki Matsutani (CANDARW, 2022)

Accelerating Distributed Deep Reinforcement Learning by In-Network Experience Sampling. - Masaki Furukawa; Hiroki Matsutani (PDP, 2022)

dsODENet: Neural ODE and Depthwise Separable Convolution for Domain Adaptation on FPGAs. - Hiroki Kawakami; Hirohisa Watanabe; Keisuke Sugiura; Hiroki Matsutani (PDP, 2022)

A Universal LiDAR SLAM Accelerator System on Low-Cost FPGA. - Keisuke Sugiura; Hiroki Matsutani (IEEE Access, 2022)

On-Device Learning: A Neural Network Based Field-Trainable Edge AI. - Hiroki Matsutani; Mineto Tsukada; Masaaki Kondo (CoRR, 2022)

A Sequential Concept Drift Detection Method for On-Device Learning on Low-End Edge Devices. - Takeya Yamada; Hiroki Matsutani (CoRR, 2022)

An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit. - Mineto Tsukada; Hiroki Matsutani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

A traffic-aware memory-cube network using bypassing. - Yoshiya Shikama; Ryuta Kawano; Hiroki Matsutani; Hideharu Amano; Yusuke Nagasaka; Naoto Fukumoto; Michihiro Koibuchi (Microprocess. Microsystems, 2022)

Performance Improvement of Federated Learning Server using Smart NIC. - Naoki Shibahara; Michihiro Koibuchi; Hiroki Matsutani (CANDARW, 2023)

A Lightweight Transformer Model using Neural ODE for FPGAs. - Ikumi Okubo; Keisuke Sugiura; Hiroki Kawakami; Hiroki Matsutani (IPDPS Workshops, 2023)

A Lightweight Concept Drift Detection Method for On-Device Learning on Resource-Limited Edge Devices. - Takeya Yamada; Hiroki Matsutani (IPDPS Workshops, 2023)

An Edge-Server Partitioning Method for 3D LiDAR SLAM on FPGAs. - Mizuki Yasuda; Keisuke Sugiura; Ryuto Kojima; Hiroki Matsutani (IPDPS Workshops, 2023)

An Efficient Accelerator for Deep Learning-based Point Cloud Registration on FPGAs. - Keisuke Sugiura; Hiroki Matsutani (PDP, 2023)

Designing low-diameter interconnection networks with multi-ported host-switch graphs. - Ryota Yasudo; Koji Nakano; Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano (Concurr. Comput. Pract. Exp., 2023)

A Case for Offloading Federated Learning Server on Smart NIC. - Naoki Shibahara; Michihiro Koibuchi; Hiroki Matsutani (CoRR, 2023)

Addressing the Gap Between Training Data and Deployed Environment by On-Device Learning. - Kazuki Sunaga; Masaaki Kondo; Hiroki Matsutani (IEEE Micro, 2023)

A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs. - Hiroki Kawakami; Hirohisa Watanabe; Keisuke Sugiura; Hiroki Matsutani (IEICE Trans. Inf. Syst., 2023)

A Lightweight Reinforcement Learning Based Packet Routing Method Using Online Sequential Learning. - Kenji Nemoto; Hiroki Matsutani (IEICE Trans. Inf. Syst., 2023)

A Tiny Supervised ODL Core with Auto Data Pruning for Human Activity Recognition. - Hiroki Matsutani; Radu Marculescu (BSN, 2024)

An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm. - Kazuki Sunaga; Keisuke Sugiura; Hiroki Matsutani (IPDPS (Workshops), 2024)

A Scalable Secure Fault Tolerant Aggregation for P2P Federated Learning. - Yujiro Yahata; Keisuke Sugiura; Hiroki Matsutani (IPDPS (Workshops), 2024)

The Case for Coherence Directories in Memory Cubes. - Yuki Kameyama; Naoya Niwa; Daichi Fujiki; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (MCSoC, 2024)

An Efficient Distributed Reinforcement Learning Architecture for Long-Haul Communication Between Actors and Learner. - Shin Morishima; Hiroki Matsutani (IEEE Access, 2024)

A Cost-Efficient FPGA-Based CNN-Transformer Using Neural ODE. - Ikumi Okubo; Keisuke Sugiura; Hiroki Matsutani (IEEE Access, 2024)

A Cost-Efficient FPGA Implementation of Tiny Transformer Model using Neural ODE. - Ikumi Okubo; Keisuke Sugiura; Hiroki Matsutani (CoRR, 2024)

Federated Learning of Neural ODE Models with Different Iteration Counts. - Yuto Hoshino; Hiroki Kawakami; Hiroki Matsutani (IEICE Trans. Inf. Syst., 2024)

A Sequential Approach to Detect Drifts and Retrain Neural Networks on Resource-Limited Edge Devices. - Kazuki Sunaga; Takeya Yamada; Hiroki Matsutani (IEICE Trans. Inf. Syst., 2024)

An Integrated FPGA Accelerator for Deep Learning-Based 2D/3D Path Planning. - Keisuke Sugiura; Hiroki Matsutani (IEEE Trans. Computers, 2024)

Data Poisoning Attack against Neural Network-Based On-Device Learning Anomaly Detector by Physical Attacks on Sensors. - Takahito Ino; Kota Yoshida; Hiroki Matsutani; Takeshi Fujino (Sensors, 2024)

Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge Devices. - Hiroki Matsutani; Masaaki Kondo; Kazuki Sunaga; Radu Marculescu (ASP-DAC, 2025)

ElasticZO: A Memory-Efficient On-Device Learning with Combined Zeroth- and First-Order Optimization. - Keisuke Sugiura; Hiroki Matsutani (CoRR, 2025)

PointODE: Lightweight Point Cloud Learning with Neural Ordinary Differential Equations on Edge. - Keisuke Sugiura; Mizuki Yasuda; Hiroki Matsutani (CoRR, 2025)

InstantFT: An FPGA-Based Runtime Subsecond Fine-tuning of CNN Models. - Keisuke Sugiura; Hiroki Matsutani (CoRR, 2025)

FPGA-accelerated Correspondence-free Point Cloud Registration with PointNet Features. - Keisuke Sugiura; Hiroki Matsutani (ACM Trans. Reconfigurable Technol. Syst., 2025)