A 1-V 1-Mb SRAM for portable equipment. - Hiroki Morimura; Nobutaro Shibata (ISLPED, 1996)

A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's. - Hiroki Morimura; Nobutaro Shibata (IEEE J. Solid State Circuits, 1998)

A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells. - Hiroki Morimura; Satoshi Shigematsu; Shinsuke Konaka (ISLPED, 1999)

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers. - Nobutaro Shibata; Hiroki Morimura; Mayumi Watanabe (IEEE J. Solid State Circuits, 1999)

A single-chip fingerprint sensor and identifier. - Satoshi Shigematsu; Hiroki Morimura; Yasuyuki Tanabe; Takuya Adachi; Katsuyuki Machida (IEEE J. Solid State Circuits, 1999)

A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors. - Hiroki Morimura; Satoshi Shigematsu; Katsuyuki Machida (IEEE J. Solid State Circuits, 2000)

1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs. - Nobutaro Shibata; Hiroki Morimura; Mitsuru Harada (IEEE J. Solid State Circuits, 2000)

A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification. - Koji Fujii; Mamoru Nakanishi; Satoshi Shigematsu; Hiroki Morimura; Takahiro Hatano; Namiko Ikeda; Toshishige Shimamura; Yukio Okazaki; Hakaru Kyuragi (CICC, 2002)

A Fingerprint Verification Algorithm Using the Differential Matching Rate. - Takahiro Hatano; Takuya Adachi; Satoshi Shigematsu; Hiroki Morimura; Shigehiko Onishi; Yukio Okazaki; Hakaru Kyuragi (ICPR (3), 2002)

A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs. - Hiroki Morimura; Satoshi Shigematsu; Toshishige Shimamura; Katsuyuki Machida; Hakaru Kyuragi (IEEE J. Solid State Circuits, 2002)

Pixel-Parallel Image-Matching Circuit Schemes for a Single-Chip Fingerprint Sensor and Identifier. - Satoshi Shigematsu; Hiroki Morimura; Katsuyuki Machida; Yukio Okazaki; Hakaru Kyuragi (IEICE Trans. Electron., 2005)

Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier. - Satoshi Shigematsu; Koji Fujii; Hiroki Morimura; Takahiro Hatano; Mamoru Nakanishi; Namiko Ikeda; Toshishige Shimamura; Katsuyuki Machida; Yukio Okazaki; Hakaru Kyuragi (IEICE Trans. Electron., 2006)

Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI. - Satoshi Shigematsu; Hiroki Morimura; Toshishige Shimamura; Takahiro Hatano; Namiko Ikeda; Yukio Okazaki; Katsuyuki Machida; Mamoru Nakanishi (IEICE Trans. Electron., 2007)

A Fingerprint Sensor with Impedance Sensing for Fraud Detection. - Toshishige Shimamura; Hiroki Morimura; Nobuhiro Shimoyama; Tomomi Sakata; Satoshi Shigematsu; Katsuyuki Machida; Mamoru Nakanishi (ISSCC, 2008)

Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications. - Toshishige Shimamura; Mamoru Ugajin; Kenji Suzuki; Kazuyoshi Ono; Norio Sato; Kei Kuwabara; Hiroki Morimura; Shin'ichiro Mutoh (ISSCC, 2010)

Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs. - Toshishige Shimamura; Hiroki Morimura; Satoshi Shigematsu; Mamoru Nakanishi; Katsuyuki Machida (IEEE J. Solid State Circuits, 2010)

1-cm3 event-driven wireless sensor nodes. - Shoichi Oshima; Kenichi Matsunaga; Toshishige Shimamura; Hiroki Morimura; Mitsuru Harada (ICCS, 2012)

Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current. - Shunji Nakata; Ryota Honda; Hiroshi Makino; Hiroki Morimura; Yoshio Matsuda (MWSCAS, 2012)

Ultra-low-power circuit techniques for mm-size wireless sensor nodes with energy harvesting. - Hiroki Morimura; Shoichi Oshima; Kenichi Matsunaga; Toshishige Shimamura; Mitsuru Harada (IEICE Electron. Express, 2014)

Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. - Shunji Nakata; Hiroki Hanazono; Hiroshi Makino; Hiroki Morimura; Masayuki Miyama; Yoshio Matsuda (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Wide Frequency PLL-less Clock Generator with Fast Intermittent Operation for Low-Power Wearable Medical Applications. - Ahmed Musa; Tadashi Minotani; Toshihiko Kondo; Hiroki Morimura (APCC, 2015)

Analysis to optimize sensitivity of RF energy harvester with voltage boost circuit. - Dan Luo; Hiroshi Fuketa; Kenichi Matsunaga; Hiroki Morimura; Makoto Takamiya; Takayasu Sakurai (ECCTD, 2015)

248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting. - Teruki Someya; Hiroshi Fuketa; Kenichi Matsunaga; Hiroki Morimura; Takayasu Sakurai; Makoto Takamiya (ESSCIRC, 2015)

An 8-mode reconfigurable sensor-independent readout circuit for trillion sensors era. - Ahmed Musa; Tadashi Minotani; Kenichi Matsunaga; Toshihiko Kondo; Hiroki Morimura (ISSNIP, 2015)

56-Level programmable voltage detector in steps of 50mV for battery management. - Teruki Someya; Kenichi Matsunaga; Hiroki Morimura; Takayasu Sakurai; Makoto Takamiya (A-SSCC, 2016)

Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier. - Teruki Someya; Hiroshi Fuketa; Kenichi Matsunaga; Hiroki Morimura; Takayasu Sakurai; Makoto Takamiya (IEICE Trans. Electron., 2017)

Analysis and Experimental Study of Magnetic-Field Amplification by a Double Coil. - Ai-ichiro Sasaki; Olivier Ouellette; Maxime Beaudry-Marchand; Akihiko Hirata; Hiroki Morimura (IEEE Trans. Ind. Electron., 2017)

A 0.90-4.39-V Detection Voltage Range, 56-Level Programmable Voltage Detector Using Fine Voltage-Step Subtraction for Battery Management. - Teruki Someya; Kenichi Matsunaga; Hiroki Morimura; Takayasu Sakurai; Makoto Takamiya (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)