A Design Algorithm for Sequential Circuits Using LUT Rings. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A fast logic simulator using a look up table cascade emulator. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ASP-DAC, 2006)

A Soft Error Tolerant LUT Cascade Emulator. - Hiroki Nakahara; Tsutomu Sasao (ATS, 2006)

A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Implementations of Reconfigurable Logic Arrays on FPGAs. - Tsutomu Sasao; Hiroki Nakahara (FPT, 2007)

A CAM Emulator Using Look-Up Table Cascades. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IPDPS, 2007)

A Parallel Branching Program Machine for Emulation of Sequential Circuits. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Yoshifumi Kawamura (ARC, 2009)

The Parallel Sieve Method for a Virus Scanning Engine. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Yoshifumi Kawamura (DSD, 2009)

A virus scanning engine using a parallel finite-input memory machine and MPUs. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Yoshifumi Kawamura (FPL, 2009)

A Quaternary Decision Diagram Machine and the Optimization of its Code. - Tsutomu Sasao; Hiroki Nakahara; Munehiro Matsuura; Yoshifumi Kawamura; Jon T. Butler (ISMVL, 2009)

A Packet Classifier Using a Parallel Branching Program Machine. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (DSD, 2010)

A Comparison of Architectures for Various Decision Diagram Machines. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2010)

A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Yoshifumi Kawamura (IEICE Trans. Inf. Syst., 2010)

A Quaternary Decision Diagram Machine: Optimization of Its Code. - Tsutomu Sasao; Hiroki Nakahara; Munehiro Matsuura; Yoshifumi Kawamura; Jon T. Butler (IEICE Trans. Inf. Syst., 2010)

A Regular Expression Matching Circuit Based on a Decomposed Automaton. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ARC, 2011)

A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2011)

A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ARC, 2012)

On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer. - Hiroki Nakahara; Hiroyuki Nakanishi; Tsutomu Sasao (ICA3PP (1), 2012)

Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2012)

A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Inf. Syst., 2012)

A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (Microprocess. Microsystems, 2012)

A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (J. Multiple Valued Log. Soft Comput., 2012)

On a wideband fast fourier transform for a radio telescope. - Hiroki Nakahara; Hiroyuki Nakanishi; Tsutomu Sasao (SIGARCH Comput. Archit. News, 2012)

An Architecture for IPv6 Lookup Using Parallel Index Generation Units. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ARC, 2013)

A packet classifier using LUT cascades based on EVMDDS (k). - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (FPL, 2013)

A high-speed FFT based on a six-step algorithm: Applied to a radio telescope for a solar radio burst. - Hiroki Nakahara; Kazumasa Iwai; Hiroyuki Nakanishi (FPT, 2013)

A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2013)

A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Inf. Syst., 2013)

Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimization. - Kenichi Ohhata; Hiroki Nakahara; Takuya Inoue; Toru Yazaki; Norio Chujo; Takuma Nishimoto (ISIC, 2014)

An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K). - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2014)

An AWF digital spectrometer for a radio telescope. - Hiroki Nakahara; Hiroyuki Nakanishi; Kazumasa Iwai (ReConFig, 2014)

A Packet Classifier Based on Prefetching EVMDD (k) Machines. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Inf. Syst., 2014)

A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (J. Multiple Valued Log. Soft Comput., 2014)

A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank. - Hiroki Nakahara; Hideki Yoshida; Shin-ich Shioya; Renji Mikami; Tsutomu Sasao (ARC, 2015)

A deep convolutional neural network based on nested residue number system. - Hiroki Nakahara; Tsutomu Sasao (FPL, 2015)

An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD. - Hiroki Nakahara; Tsutomu Sasao; Hiroyuki Nakanishi; Kazumasa Iwai (ISMVL, 2015)

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Hisashi Iwamoto; Yasuhiro Terao (IEICE Trans. Inf. Syst., 2015)

An acceleration of a random forest classification using Altera SDK for OpenCL. - Hiroki Nakahara; Akira Jinguji; Tomonori Fujii; Simpei Sato (FPT, 2016)

A memory-based realization of a binarized deep convolutional neural network. - Hiroki Nakahara; Haruyoshi Yonekawa; Tsutomu Sasao; Hisashi Iwamoto; Masato Motomura (FPT, 2016)

An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope. - Hiroki Nakahara; Tsutomu Sasao; Hiroyuki Nakanishi; Kazumasa Iwai; Tohru Nagao; Naoya Ogawa (ISMVL, 2016)

LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification. - Hiroki Nakahara; Tsutomu Sasao; Hisashi Iwamoto; Munehiro Matsuura (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k). - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Hisashi Iwamoto (J. Multiple Valued Log. Soft Comput., 2016)

An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division. - Hiroki Nakahara; Hiroyuki Nakanishi; Kazumasa Iwai; Tsutomu Sasao (SIGARCH Comput. Archit. News, 2016)

An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning. - Tomoya Fujii; Simpei Sato; Hiroki Nakahara; Masato Motomura (ARC, 2017)

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). - Hiroki Nakahara; Haruyoshi Yonekawa; Hisashi Iwamoto; Masato Motomura (FPGA, 2017)

A fully connected layer elimination for a binarizec convolutional neural network on an FPGA. - Hiroki Nakahara; Tomoya Fujii; Shimpei Sato (FPL, 2017)

An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA. - Hiroki Nakahara; Haruyoshi Yonekawa; Shimpei Sato (FPT, 2017)

All binarized convolutional neural network and its implementation on an FPGA. - Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (FPT, 2017)

On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA. - Haruyoshi Yonekawa; Hiroki Nakahara (IPDPS Workshops, 2017)

A Random Forest Using a Multi-valued Decision Diagram on an FPGA. - Hiroki Nakahara; Akira Jinguji; Simpei Sato; Tsutomu Sasao (ISMVL, 2017)

In-memory area-efficient signal streaming processor design for binary neural networks. - Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Kota Ando; Kodai Ueyoshi; Kazutoshi Hirose; Kentaro Orimo; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (MWSCAS, 2017)

Hardware Algorithms. - Kentaro Sano; Hiroki Nakahara (Principles and Structures of FPGAs, 2018)

A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. - Hiroki Nakahara; Haruyoshi Yonekawa; Tomoya Fujii; Shimpei Sato (FPGA, 2018)

A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). - Hiroki Nakahara; Masayuki Shimoda; Shimpei Sato (FPL, 2018)

Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. - Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (FPL, 2018)

An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network. - Akira Jinguji; Tomoya Fujii; Shimpei Sato; Hiroki Nakahara (FPT, 2018)

A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. - Hiroki Nakahara; Masayuki Shimoda; Shimpei Sato (FPT, 2018)

A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS). - Haoxuan Cheng; Shimpei Sato; Hiroki Nakahara (HEART, 2018)

Power Efficient Object Detector with an Event-Driven Camera on an FPGA. - Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (HEART, 2018)

A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector. - Hiroki Nakahara; Tsutomu Sasao (ISCAS, 2018)

A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor. - Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara (ISMVL, 2018)

New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications. - Taro Fujii; Takao Toi; Teruhito Tanaka; Katsumi Togawa; Toshiro Kitaoka; Kengo Nishino; Noritsugu Nakamura; Hiroki Nakahara; Masato Motomura (VLSI Circuits, 2018)

A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA. - Tomoya Fujii; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2018)

An FPGA Realization of a Random Forest with k-Means Clustering Using a High-Level Synthesis Design. - Akira Jinguji; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2018)

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. - Kota Ando; Kodai Ueyoshi; Kentaro Orimo; Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2018)

Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation. - Masayuki Shimoda; Youki Sada; Hiroki Nakahara (ARC, 2019)

An FPGA-based Fine Tuning Accelerator for a Sparse CNN. - Hiroki Nakahara; Akira Jinguji; Masayuki Shimoda; Shimpei Sato (FPGA, 2019)

Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA. - Akira Jinguji; Youki Sada; Hiroki Nakahara (FPL, 2019)

FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. - Hiroki Nakahara; Youki Sada; Masayuki Shimoda; Kouki Sayama; Akira Jinguji; Shimpei Sato (FPL, 2019)

An FPGA Implementation of Real-Time Object Detection with a Thermal Camera. - Masayuki Shimoda; Youki Sada; Ryosuke Kuramochi; Hiroki Nakahara (FPL, 2019)

A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA. - Youki Sada; Masayuki Shimoda; Akira Jinguji; Hiroki Nakahara (FPT, 2019)

Noise Convolutional Neural Networks and FPGA Implementation. - Atsuki Munakata; Hiroki Nakahara; Shimpei Sato (ISMVL, 2019)

Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. - Ryosuke Kuramochi; Youki Sada; Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (MCSoC, 2019)

FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. - Ryosuke Kuramochi; Masayuki Shimoda; Youki Sada; Shimpei Sato; Hiroki Nakahara (ReConFig, 2019)

GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. - Hiroki Nakahara; Haruyoshi Yonekawa; Tomoya Fujii; Masayuki Shimoda; Shimpei Sato (IEICE Trans. Inf. Syst., 2019)

Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. - Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2019)

Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs. - Akira Jinguji; Shimpei Sato; Hiroki Nakahara (FCCM, 2020)

High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression. - Hiroki Nakahara; Zhiqiang Que; Wayne Luk (FCCM, 2020)

Optimizing Reconfigurable Recurrent Neural Networks. - Zhiqiang Que; Hiroki Nakahara; Eriko Nurvitadhi; Hongxiang Fan; Chenglong Zeng; Jiuxi Meng; Xinyu Niu; Wayne Luk (FCCM, 2020)

R2CNN: Recurrent Residual Convolutional Neural Network on FPGA. - Hiroki Nakahara; Zhiqiang Que; Akira Jinguji; Wayne Luk (FPGA, 2020)

An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks. - Ryosuke Kuramochi; Hiroki Nakahara (FPL, 2020)

A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. - Zhiqiang Que; Hiroki Nakahara; Hongxiang Fan; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Eriko Nurvitadhi; Wayne Luk (FPT, 2020)

Design Method for an LUT Network-Based CNN with a Sparse Local Convolution. - Naoto Soga; Hiroki Nakahara (FPT, 2020)

Fast Monocular Depth Estimation on an FPGA. - Youki Sada; Naoto Soga; Masayuki Shimoda; Akira Jinguji; Shimpei Sato; Hiroki Nakahara (IPDPS Workshops, 2020)

2n+1-valued SSS-Net: Uniform Shift, Channel Sparseness, and Channel Shuffle. - Hiroki Nakahara (ISMVL, 2020)

A Table Look-Up Based Ternary Neural Network Processor. - Yuta Suzuki; Naoto Soga; Shimpei Sato; Hiroki Nakahara (ISMVL, 2020)

SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. - Masayuki Shimoda; Youki Sada; Ryosuke Kuramochi; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2020)

Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. - Kota Ando; Jaehoon Yu; Kazutoshi Hirose; Hiroki Nakahara; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (HCS, 2021)

A High-Throughput Detection Circuit based on 2q+1-Valued Deep Neural Networks. - Naoto Soga; Ryosuke Kuramochi; Hiroki Nakahara (ISMVL, 2021)

Detection of Wrong Direction Vehicles on Two-Way Traffic. - Pintusorn Suttiponpisarn; Chalermpol Charnsripinyo; Sasiporn Usanavasin; Hiroki Nakahara (KSE, 2021)

A novel compact planar magic-T using CPS and microstrip-to-CPS transition. - Hiroki Nakahara; Takayuki Tanaka; Ichihiko Toyoda (IEICE Electron. Express, 2021)

Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs. - Akira Jinguji; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2021)

A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA. - Ryosuke Kuramochi; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2021)

Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder. - Naoto Soga; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2021)

FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling. - Masayuki Shimoda; Youki Sada; Hiroki Nakahara (J. Signal Process. Syst., 2021)

Preface. - Yun Liang 001; Hiroki Nakahara; Wei Zhang 012; Fubing Mao; Ray C. C. Cheung (FPT, 2022)

Message from the General Chair and Program Co-Chairs. - Wei Zhang 012; Ray C. C. Cheung; Yun Liang 001; Hiroki Nakahara (FPT, 2022)

Fast Interface with Ensemble Ternary Neural Network. - Ryota Kayanoma; Hiroki Nakahara (ISMVL, 2022)

Optimizations of Ternary Generative Adversarial Networks. - Kennichi Nakamura; Hiroki Nakahara (ISMVL, 2022)

Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. - Zhiqiang Que; Hiroki Nakahara; Eriko Nurvitadhi; Andrew Boutros; Hongxiang Fan; Chenglong Zeng; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Multilayer Perceptron Training Accelerator Using Systolic Array. - Takeshi Senoo; Akira Jinguji; Ryosuke Kuramochi; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2022)

A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGA. - Takeshi Senoo; Ryota Kayanoma; Akira Jinguji; Hiroki Nakahara (ARC, 2023)

A Consideration on Ternary Adversarial Generative Networks. - Kennichi Nakamura; Hiroki Nakahara (ISMVL, 2023)

A Many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference. - Ryota Kayanoma; Akira Jinguji; Hiroki Nakahara (MCSoC, 2023)

Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. - Zhiqiang Que; Hiroki Nakahara; Hongxiang Fan; He Li 008; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Eriko Nurvitadhi; Wayne Luk (ACM Trans. Reconfigurable Technol. Syst., 2023)

A Table Look-Up Based Quantum Simulation Accelerator on an FPGA. - Haruhiko Hasegawa; Masayuki Shimoda; Hiroki Nakahara; Takefumi Miyoshi (ICFPT, 2024)

A Weight Ternary Ensemble Vision Transformer Toward Memory Size Reduction. - Ryota Kayanoma; Hiroki Nakahara (ISMVL, 2024)

A Stacked FPGA utilizing 3D-SRAM with Latency Optimization. - Ryo Takahashi; Kota Ando; Hiroki Nakahara (MCSoC, 2024)

A Novel Data Representation Towards Efficient FPGA-based Quantum Computer Simulation. - Haruhiko Hasegawa; Masayuki Shimoda; Hiroki Nakahara; Takefumi Miyoshi (ISMVL, 2025)