A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Kentaro Kawakami; Junichi Miyakoshi; Shinji Mikami; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. - Hiroki Noguchi; Yusuke Iguchi; Hidehiro Fujiwara; Yasuhiro Morita; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISVLSI, 2007)

Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Yusuke Iguchi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Yusuke Iguchi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2007)

A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system. - Kazuo Miura; Hiroki Noguchi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (FPT, 2008)

Quality of a Bit (QoB): A New Concept in Dependable SRAM. - Hidehiro Fujiwara; Shunsuke Okumura; Yusuke Iguchi; Hiroki Noguchi; Yasuhiro Morita; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2008)

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. - Hiroki Noguchi; Yusuke Iguchi; Hidehiro Fujiwara; Shunsuke Okumura; Yasuhiro Morita; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2008)

Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. - Hidehiro Fujiwara; Koji Nii; Hiroki Noguchi; Junichi Miyakoshi; Yuichiro Murachi; Yasuhiro Morita; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system. - Tsuyoshi Fujinaga; Kazuo Miura; Hiroki Noguchi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (INTERSPEECH, 2009)

A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. - Shunsuke Okumura; Yusuke Iguchi; Shusuke Yoshimoto; Hidehiro Fujiwara; Hiroki Noguchi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2009)

An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks. - Hiroki Noguchi; Tomoya Takagi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (SiPS, 2009)

A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. - Hidehiro Fujiwara; Shunsuke Okumura; Yusuke Iguchi; Hiroki Noguchi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (VLSI Design, 2009)

A Dependable SRAM with 7T/14T Memory Cells. - Hidehiro Fujiwara; Shunsuke Okumura; Yusuke Iguchi; Hiroki Noguchi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2009)

A 34.7-mW quad-core MIQP solver processor for robot control. - Hiroki Noguchi; Junichi Tani; Yusuke Shimai; Masanori Nishino; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2010)

Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video. - Kosuke Mizuno; Hiroki Noguchi; Guangji He; Yosuke Terachi; Tetsuya Kamino; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (FPL, 2010)

Live demonstration: Intelligent ubiquitous sensor network for sound acquisition. - Koji Kugata; Tomoya Takagi; Hiroki Noguchi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ISCAS, 2010)

Intelligent ubiquitous sensor network for sound acquisition. - Koji Kugata; Tomoya Takagi; Hiroki Noguchi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ISCAS, 2010)

Parallel-processing VLSI architecture for mixed integer linear programming. - Hiroki Noguchi; Junichi Tani; Yusuke Shimai; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISCAS, 2010)

A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition. - Guangji He; Takanobu Sugahara; Tsuyoshi Fujinaga; Yuki Miyamoto; Hiroki Noguchi; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2011)

Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network. - Shintaro Izumi; Hiroki Noguchi; Tomoya Takagi; Koji Kugata; Shinpei Soda; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ICCCN, 2011)

0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM. - Hiroki Noguchi; Shunsuke Okumura; Tomoya Takagi; Koji Kugata; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ISQED, 2011)

A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition. - Kosuke Mizuno; Hiroki Noguchi; Guangji He; Yosuke Terachi; Tetsuya Kamino; Tsuyoshi Fujinaga; Shintaro Izumi; Yasuo Ariki; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2011)

VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition. - Hiroki Noguchi; Kazuo Miura; Tsuyoshi Fujinaga; Takanobu Sugahara; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2011)

Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. - Hiroki Noguchi; Yusuke Iguchi; Hidehiro Fujiwara; Shunsuke Okumura; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Data-Intensive Sound Acquisition System with Large-scale Microphone Array. - Hiroki Noguchi; Tomoya Takagi; Koji Kugata; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (J. Inf. Process., 2011)

A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition. - Guangji He; Takanobu Sugahara; Yuki Miyamoto; Tsuyoshi Fujinaga; Hiroki Noguchi; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. - Hiroki Noguchi; Kumiko Nomura; Keiko Abe; Shinobu Fujita; Eishi Arima; Kyundong Kim; Takashi Nakada; Shinobu Miwa; Hiroshi Nakamura (DATE, 2013)

Novel nonvolatile memory hierarchies to realize "normally-off mobile processors". - Shinobu Fujita; Kumiko Nomura; Hiroki Noguchi; Susumu Takeda; Keiko Abe (ASP-DAC, 2014)

Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. - Shinobu Fujita; Hiroki Noguchi; Kazutaka Ikegami; Susumu Takeda; Kumiko Nomura; Keiko Abe (ISIC, 2014)

Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU. - Hiroki Noguchi; Kazutaka Ikegami; Naoharu Shimomura; Tetsufumi Tanamoto; Junichi Ito; Shinobu Fujita (VLSIC, 2014)

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. - Eishi Arima; Hiroki Noguchi; Takashi Nakada; Shinobu Miwa; Susumu Takeda; Shinobu Fujita; Hiroshi Nakamura (ICCD, 2015)

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. - Hiroki Noguchi; Kazutaka Ikegami; Keiichi Kushida; Keiko Abe; Shogo Itai; Satoshi Takaya; Naoharu Shimomura; Junichi Ito; Atsushi Kawasumi; Hiroyuki Hara; Shinobu Fujita (ISSCC, 2015)

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. - Hiroki Noguchi; Kazutaka Ikegami; Satoshi Takaya; Eishi Arima; Keiichi Kushida; Atsushi Kawasumi; Hiroyuki Hara; Keiko Abe; Naoharu Shimomura; Junichi Ito; Shinobu Fujita; Takashi Nakada; et al. (ISSCC, 2016)

Novel memory hierarchy with e-STT-MRAM for near-future applications. - Shinobu Fujita; Hiroki Noguchi; Kazutaka Ikegami; Susumu Takeda; Kumiko Nomura; Keiko Abe (VLSI-DAT, 2017)

Network theory-based accident scenario analysis for hazardous material transport: A case study of liquefied petroleum gas transport in japan. - Hiroki Noguchi; Shunichi Hienuki; Masaaki Fuse (Reliab. Eng. Syst. Saf., 2020)

RoboCup2022 KidSize League Winner CIT Brains: Open Platform Hardware SUSTAINA-OP and Software. - Yasuo Hayashibara; Masato Kubotera; Hayato Kambe; Gaku Kuwano; Dan Sato; Hiroki Noguchi; Riku Yokoo; Satoshi Inoue; Yuta Mibuchi; Kiyoshi Irie (RoboCup, 2022)

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes. - Ku-Feng Lin; Hiroki Noguchi; Yi-Chun Shih; Perng-Fei Yuh; Yuan-Jen Lee; Tung-Cheng Chang; Sheng-Po Huang; Yu-Fan Lin; Chun-Ying Lee; Yen-Hsiang Huang; Jui-Che Tsai; Saman Adham; et al. (ISSCC, 2024)

Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. - Xiaoyu Sun 001; Weidong Cao 001; Brian Crafton; Kerem Akarvardar; Haruki Mori; Hidehiro Fujiwara; Hiroki Noguchi; Yu-Der Chih; Meng-Fan Chang; Yih Wang; Tsung-Yung Jonathan Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)