Analysis and Design of a Current-Mode PWM Buck Converter Adopting the Output-Voltage Independent Second-Order Slope Compensation Scheme. - Hiroki Sakurai; Yasuhiro Sugimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A CMOS Current-mode DC-DC converter with input and output voltage-independent stability and frequency characteristics utilizing a quadratic slope compensation scheme. - Kiyokazu Umimura; Hiroki Sakurai; Yasuhiro Sugimoto (ESSCIRC, 2007)

The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25 V of Output Voltage Using a Fractional VBE Amplification Scheme. - Hiroki Sakurai; Yasuhiro Sugimoto (IEICE Trans. Electron., 2007)

A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture. - Hiroki Sakurai; Shigeto Tanaka; Yasuhiro Sugimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A 1.5GHz-modulation-range 10ms-modulation-period 180kHzrms-frequency-error 26MHz-reference mixed-mode FMCW synthesizer for mm-wave radar application. - Hiroki Sakurai; Yuka Kobayashi; Toshiya Mitomo; Osamu Watanabe 003; Shoji Otaka (ISSCC, 2011)

A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS. - Daisuke Miyashita; Kenichi Agawa; Hirotsugu Kajihara; Kenichi Sami; Masaomi Iwanaga; Yosuke Ogasawara; Tomohiko Ito; Daisuke Kurose; Naotaka Koide; Toru Hashimoto; Hiroki Sakurai; Takafumi Yamaji; et al. (VLSIC, 2012)

Gender-Dependent Babble Maskers Created from Multi-speaker Speech for Speech Privacy Protection. - Kazuhiro Kondo; Hiroki Sakurai (IIH-MSP, 2014)

An 18 µW spur canceled clock generator for recovering receiver sensitivity in wireless SoCs. - Yosuke Ogasawara; Hiroki Sakurai; Ryuichi Fujimoto; Kenichi Sami (VLSI Circuits, 2016)