A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. - Narumi Sakashita; Fumihiro Okuda; Ken'ichi Shimomura; Hiroki Shimano; Mitsuhiro Hamada; Tetsuo Tada; Shinji Komori; Kazuo Kyuma; Akihiko Yasuoka; Haruhiko Abe (ITC, 1996)

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. - Narumi Sakashita; Yasuhiko Nitta; Ken'ichi Shimomura; Fumihiro Okuda; Hiroki Shimano; Satoshi Yamakawa; Masaki Tsukude; Kazutami Arimoto; Shinji Baba; Shinji Komori; Kazuo Kyuma; Akihiko Yasuoka; et al. (IEEE J. Solid State Circuits, 1996)

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. - Ken'ichi Shimomura; Hiroki Shimano; Narumi Sakashita; Fumihiro Okuda; Toshiyuki Oashi; Yasuo Yamaguchi; Takahisa Eimori; Masahide Inuishi; Kazutami Arimoto; Shigeto Maegawa; Yasuo Inoue; Shinji Komori; et al. (IEEE J. Solid State Circuits, 1997)

A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. - Hiroki Shimano; Fukashi Morishita; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2007)

A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. - Kazutami Arimoto; Fukashi Morishita; Isamu Hayashi; Katsumi Dosaka; Hiroki Shimano; Takashi Ipposhi (IEEE J. Solid State Circuits, 2007)

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. - Fukashi Morishita; Isamu Hayashi; Takayuki Gyohten; Hideyuki Noda; Takashi Ipposhi; Hiroki Shimano; Katsumi Dosaka; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. - Hiroki Shimano; Fukashi Morishita; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2009)