3-D Range Map Acquisition System Based on CMOS Image Sensor Using Time-Multiplexing Structured Pattern. - Hiroki Yabe; Makoto Ikeda (IEICE Trans. Electron., 2012)

11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology. - Ryuji Yamashita; Sagar Magia; Tsutomu Higuchi; Kazuhide Yoneya; Toshio Yamamura; Hiroyuki Mizukoshi; Shingo Zaitsu; Minoru Yamashita; Shunichi Toyama; Norihiro Kamae; Juan Lee; Shuo Chen; et al. (ISSCC, 2017)

13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs. - Toshiyuki Kouchi; Noriyasu Kumazaki; Masashi Yamaoka; Sanad Bushnaq; Takuyo Kodama; Yuki Ishizaki; Yoko Deguchi; Akio Sugahara; Akihiro Imamoto; Norichika Asaoka; Ryosuke Isomura; Takaya Handa; et al. (ISSCC, 2020)

A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs. - Toshiyuki Kouchi; Mami Kakoi; Noriyasu Kumazaki; Akio Sugahara; Akihiro Imamoto; Yasufumi Kajiyama; Yuri Terada; Sanad Bushnaq; Naoaki Kanagawa; Takuyo Kodama; Ryo Fukuda; Hiromitsu Komai; et al. (IEEE J. Solid State Circuits, 2021)

A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm2 bit density with 3.2Gbps interface and 205MB/s program throughput. - Mario Sako; T. Nakajima; Fumihiro Kono; Takeshi Nakano; Masaki Fujiu; Junji Musha; Dai Nakamura; Naoaki Kanagawa; Yutaka Shimizu; Kosuke Yanagidaira; Tetsuaki Utsumi; T. Kawano; et al. (VLSI Technology and Circuits, 2023)

Crossed Bit Line (CBL) Architecture in 3D Flash Memory CMOS Directly Bonded to Array (CBA) Structure. - Hiroshi Maejima; Katsuaki Isobe; N. Okada; Masaki Unno; T. Hashimoto; Tetsuaki Utsumi; T. Hisada; K. Maruyama; Toshiyuki Kouchi; T. Kotani; Hitoshi Shiga; O. Kwon; et al. (IMW, 2025)