A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking. - Yoshio Miki; Tatsuya Saito; Hiroki Yamashita; Fumio Yuki; Takashige Baba; Akio Koyama; Masahito Sonehara (IEEE J. Solid State Circuits, 2004)

A 1.2Gb/s write driver with pre-emphasis overshoot control optimized for high density HDD applications. - Y. Hayashi; Masahito Sonehara; S. Ueno; Y. Ito; Akio Koyama; Hiroki Yamashita (CICC, 2005)

A Low-Power Write Driver for Hard Disk Drives. - Tatsuya Kawashimo; Hiroki Yamashita; Masayoshi Yagyu; Fumio Yuki (IEICE Trans. Electron., 2006)

An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane. - Koji Fukuda; Hiroki Yamashita; Fumio Yuki; Masayoshi Yagyu; Ryo Nemoto; Takashi Takemoto; Tatsuya Saito; Norio Chujo; Keiichi Yamamoto; Hisaaki Kanai; Atsuhiro Hayashi (ISSCC, 2008)

10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1st-order ΔΣ modulator. - Koji Fukuda; Hiroki Yamashita; Fumio Yuki; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Tatsuya Saito (ISSCC, 2009)

A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS. - Koji Fukuda; Hiroki Yamashita; Fumio Yuki; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Masashi Kono; Tatsuya Saito (IEEE J. Solid State Circuits, 2009)

A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS. - Takashi Takemoto; Fumio Yuki; Hiroki Yamashita; Shinji Tsuji; Tatsuya Saito; Shinji Nishimura (CICC, 2010)

A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS. - Koji Fukuda; Hiroki Yamashita; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Tatsuya Saito (ISSCC, 2010)

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process. - Koji Fukuda; Hiroki Yamashita; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Noboru Masuda; Takashi Takemoto; Fumio Yuki; Tatsuya Saito (IEEE J. Solid State Circuits, 2010)

10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (ISSCC, 2011)

A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (IEEE J. Solid State Circuits, 2011)

A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS. - Takashi Takemoto; Hiroki Yamashita; Takehito Kamimura; Fumio Yuki; Noboru Masuda; Hidehiro Toyoda; Norio Chujo; Kenji Kogo; Yong Lee; Shinji Tsuji; Shinji Nishimura (VLSIC, 2012)

High-frequency circuit design for 25 Gb/s×4 optical transceiver. - Norio Chujo; Takashi Takemoto; Fumio Yuki; Hiroki Yamashita (ASP-DAC, 2013)

A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects. - Takashi Takemoto; Hiroki Yamashita; Toru Yazaki; Norio Chujo; Yong Lee; Yasunobu Matsuoka (ISSCC, 2013)

A 25-Gb/s × 4-Ch, 8 × 8 mm2, 2.8-mm thick compact optical transceiver module for on-board optical interconnect. - Norio Chujo; Toru Yazaki; Toshiaki Takai; Daichi Kawamura; Yasunobu Matsuoka; Yong Lee; Toshiki Sugawara; Hiroki Yamashita; Takashi Takemoto; Yoshiaki Ishigami; Kinya Yamazaki; Yoshinori Sunaga; et al. (OFC/NFOEC, 2013)

Compact and power-efficient 100-Gbps CMOS-based transceiver. - Takashi Takemoto; Hiroki Yamashita; Fumio Yuki; Shinji Tsuji; Yong Lee; Koichiro Adachi; Kazunori Shinoda; Yasunobu Matsuoka; Toshiki Sugawara; Shinji Nishimura; Norio Chujo; Masaaki Nido; et al. (OFC/NFOEC, 2013)

25-Gbps×4 optical transmitter with adjustable asymmetric pre-emphasis in 65-nm CMOS. - Toru Yazaki; Norio Chujo; Hiroki Yamashita; Takashi Takemoto; Yong Lee; Yasunobu Matsuoka (ISCAS, 2014)

A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects. - Takashi Takemoto; Hiroki Yamashita; Toru Yazaki; Norio Chujo; Yong Lee; Yasunobu Matsuoka (IEEE J. Solid State Circuits, 2014)

A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion. - Takashi Takemoto; Hiroki Yamashita; Fumio Yuki; Noboru Masuda; Hidehiro Toyoda; Norio Chujo; Yong Lee; Shinji Tsuji; Shinji Nishimura (IEEE J. Solid State Circuits, 2014)

An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnects. - Takashi Takemoto; Hiroki Yamashita; Yasunobu Matsuoka; Yong Lee; Masaru Kokubo (CICC, 2015)

A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver. - Takashi Takemoto; Yasunobu Matsuoka; Yoshikazu Sugiyama; Hidenori Yonezawa; Hiroki Yamashita; Koichiro Adachi; Takahiro Nakamura; Etsuko Nomoto; Kouji Nakahara; Hideo Arimoto; Kenichi Osada; Tatemi Ido (OFC, 2015)

Enhancing low-light color images using an RGB-NIR single sensor. - Hiroki Yamashita; Daisuke Sugimura; Takayuki Hamamoto (VCIP, 2015)

Enhancing Color Images of Extremely Low Light Scenes Based on RGB/NIR Images Acquisition With Different Exposure Times. - Daisuke Sugimura; Takuya Mikami; Hiroki Yamashita; Takayuki Hamamoto (IEEE Trans. Image Process., 2015)

A jitter-reduction packaging structure for a 56-Gb/s NRZ modulated optical receiver. - Takashi Takemoto; Yasunobu Matsuoka; Hiroki Yamashita; Yong Lee; Kenichi Akita; Hideo Arimoto; Masaru Kokubo (OFC, 2016)

A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technology. - Takashi Takemoto; Yasunobu Matsuoka; Hiroki Yamashita; Yong Lee; Kenichi Akita; Hideo Arimoto; Masaru Kokubo; Tatemi Ido (VLSI Circuits, 2016)

A 50-Gb/s Optical Transmitter Based on a 25-Gb/s-Class DFB-LD and a 0.18-µm SiGe BiCMOS LD Driver. - Takashi Takemoto; Yasunobu Matsuoka; Hiroki Yamashita; Takahiro Nakamura; Yong Lee; Hideo Arimoto; Tatemi Ido (IEICE Trans. Electron., 2016)

RGB-NIR imaging with exposure bracketing for joint denoising and deblurring of low-light color images. - Hiroki Yamashita; Daisuke Sugimura; Takayuki Hamamoto (ICASSP, 2017)

Low-light color image enhancement via iterative noise reduction using RGB/NIR sensor. - Hiroki Yamashita; Daisuke Sugimura; Takayuki Hamamoto (J. Electronic Imaging, 2017)

25-Gbps 3-mW/Gbps/ch VCSEL Driver Circuit in 65-nm CMOS for Multichannel Optical Transmitter. - Toru Yazaki; Norio Chujo; Takeshi Takemoto; Hiroki Yamashita; Akira Hyogo (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-µm SiGe BiCMOS Technology. - Takashi Takemoto; Yasunobu Matsuoka; Hiroki Yamashita; Yong Lee; Hideo Arimoto; Masaru Kokubo; Tatemi Ido (IEEE J. Solid State Circuits, 2018)

Approaching Behavior Analysis for Improving a Mobile Communication Robot in a Nursing Home. - Misato Nihei; Mio Nakamura; Kohei Ikeda; Kazuki Kawamura; Hiroki Yamashita; Minoru Kamata (HCI (44), 2020)

Highly Scalable Metal Induced Lateral Crystallization (MILC) Techniques for Vertical Si Channel in Ultra-High (> 300 Layers) 3D Flash Memory. - Noritaka Ishihara; Yusuke Shimada; Takamitsu Ochi; Satoshi Seto; Haruki Matsuo; Hiroki Yamashita; Sho Morita; Masafumi Ukishima; K. Uejima; Yusuke Arayashiki; Suzuka Kajiwara; Akiyuki Murayama; et al. (VLSI Technology and Circuits, 2023)