ASIC design of a low-complexity K-best Viterbi decoder for IoT applications. - Hiromasa Kato; Thi Hong Tran; Yasuhiko Nakashima (APCCAS, 2016)

CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis. - Hiromasa Kato; Satoshi Shimaya; Keisuke Fujimoto; Tomoya Kameda; Thi Hong Tran; Shinya Takamaeda-Yamazaki; Yasuhiko Nakashima (CANDAR, 2016)