A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations. - Akira Katsuno; Hiromasa Takahashi; Hajime Kubosawa; Tomio Sato; Atsuhiro Suga; Gensuke Goto (ICCD, 1990)

The μVP 64-bit vector coprocessor: a new implementation of high-performance numerical computation. - Makoto Awaga; Hiromasa Takahashi (IEEE Micro, 1993)

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications. - Hajime Kubosawa; Hiromasa Takahashi; Satoshi Ando; Yoshimi Asada; Akira Asato; Atsuhiro Suga; Michihide Kimura; Naoshi Higaki; Hideo Miyake; Tomio Sato; Hideaki Anbutsu; Toshitaka Tsuda; et al. (IEEE J. Solid State Circuits, 1998)

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. - Hajime Kubosawa; Naoshi Higaki; Satoshi Ando; Hiromasa Takahashi; Yoshimi Asada; Hideaki Anbutsu; Tomio Sato; Masato Sakate; Atsuhiro Suga; Michihide Kimura; Hideo Miyake; Hiroshi Okano; et al. (IEEE J. Solid State Circuits, 1999)

Autonomous decentralized control for formation of multiple mobile robots considering ability of robot. - Hiromasa Takahashi; Hiroaki Nishi; Kouhei Ohnishi (IEEE Trans. Ind. Electron., 2004)

SPRAM (SPin-transfer torque RAM) design and its impact on digital systems. - Takayuki Kawahara; Riichiro Takemura; Hiromasa Takahashi; Hideo Ohno (ICECS, 2007)

2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. - Takayuki Kawahara; Riichiro Takemura; Katsuya Miura; Jun Hayakawa; Shoji Ikeda; Young Min Lee; Ryutaro Sasaki; Yasushi Goto; Kenchi Ito; Toshiyasu Meguro; Fumihiro Matsukura; Hiromasa Takahashi; et al. (ISSCC, 2007)

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. - Takayuki Kawahara; Riichiro Takemura; Katsuya Miura; Jun Hayakawa; Shoji Ikeda; Young Min Lee; Ryutaro Sasaki; Yasushi Goto; Kenchi Ito; Toshiyasu Meguro; Fumihiro Matsukura; Hiromasa Takahashi; et al. (IEEE J. Solid State Circuits, 2008)

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. - Riichiro Takemura; Takayuki Kawahara; Katsuya Miura; Hiroyuki Yamamoto; Jun Hayakawa; Nozomu Matsuzaki; Kazuo Ono; Michihiko Yamanouchi; Kenchi Ito; Hiromasa Takahashi; Shoji Ikeda; Haruhiro Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)

A vector coprocessor architecture for embedded systems. - Yi Ge; Yoshimasa Takebe; Masahiko Toichi; Makoto Mouri; Makiko Ito; Yoshio Hirose; Hiromasa Takahashi (ISOCC, 2011)

Can players avoid the tragedy of the commons in a joint debt game? - Hiromasa Takahashi; Toru Takemoto; Akihiro Suzuki (Int. J. Game Theory, 2020)

Cheating, Trust and Social Norms: Data from Germany, Vietnam, China, Taiwan, and Japan. - Toan Luu Duc Huynh; Marc Oliver Rieger; Mei Wang; David Berens; Duy-Linh Bui; Hung-Ling Chen; Tobias Peter Emering; Sen Geng; Yang Liu-Gerhards; Thomas Neumann 010; Thanh Dac Nguyen; Thong Trung Nguyen; et al. (Data, 2022)

Conducting an Experiment at Multiple Sites with Small Subject Pools: How is Raven Score Effective as a Covariate? - Kazuhito Ogawa; Yusuke Osaki; Tetsuya Kawamura; Hiromasa Takahashi; Satoshi Taguchi; Yoichiro Fujii; Kengo Kurosaka; Kohei Iyori; Naoki Watanabe 001 (IEEE Big Data, 2023)