The circuit design of the synergistic processor element of a CELL processor. - Osamu Takahashi; Russ Cook; Scott R. Cottier; Sang H. Dhong; Brian K. Flachs; Koji Hirairi; Atsushi Kawasumi; Hiroaki Murakami; Hiromi Noro; Hwa-Joon Oh; S. Onish; Juergen Pille; et al. (ICCAD, 2005)

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. - Brian K. Flachs; Shigehiro Asano; Sang H. Dhong; H. Peter Hofstee; Gilles Gervais; Roy Kim; Tien Le; Peichun Liu; Jens Leenstra; John S. Liberty; Brad W. Michael; Hwa-Joon Oh; et al. (IBM J. Res. Dev., 2007)

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI. - Osamu Takahashi; Chad Adams; D. Ault; Erwin Behnen; O. Chiang; Scott R. Cottier; Paula K. Coulman; James Culp; Gilles Gervais; M. S. Gray; Y. Itaka; C. J. Johnson; et al. (ISSCC, 2008)

23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture. - Kwangmyoung Rho; Kenji Tsuchida; Dongkeun Kim; Yutaka Shirai; Jihyae Bae; Tsuneo Inaba; Hiromi Noro; Hyunin Moon; Sungwoong Chung; Kazumasa Sunouchi; Jinwon Park; Kiseon Park; et al. (ISSCC, 2017)