A 32 kbyte integrated cache memory. - Kazuhiro Sawada; Takayasu Sakurai; Kazutaka Nogami; Tsukasa Shirotori; Toshinari Takayanagi; Tetsuya Iizuka; Takeo Maeda; Jinichi Matsunaga; Hiromichi Fuji; Kenji Maeguchi; Kiyoshi Kobayashi; Tomoyuki Ando; et al. (IEEE J. Solid State Circuits, 1989)

A video codec LSI for high-definition TV systems with one-transistor DRAM line memories. - Tomoji Takada; Takeshi Oto; Kazukuni Kitagaki; Naoyuki Hatanaka; Tatsuhiko Demura; Hiromichi Fuji; Toshinori Odaka; Hiroshi Sue; Tadahiro Oku (IEEE J. Solid State Circuits, 1989)