Human-robot cooperation in arrangement of objects using confidence measure of neuro-dynamical system. - Hiromitsu Awano; Tetsuya Ogata; Shun Nishide; Toru Takahashi 001; Kazunori Komatani; Hiroshi G. Okuno (SMC, 2010)

Use of a Sparse Structure to Improve Learning Performance of Recurrent Neural Networks. - Hiromitsu Awano; Shun Nishide; Hiroaki Arie; Jun Tani; Toru Takahashi 001; Hiroshi G. Okuno; Tetsuya Ogata (ICONIP (3), 2011)

Statistical aging under dynamic voltage scaling: A logarithmic model approach. - Jyothi Velamala; Ketul Sutaria; Hirofumi Shimizu; Hiromitsu Awano; Takashi Sato 001; Yu Cao 001 (CICC, 2012)

Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices. - Takashi Sato 001; Hiromitsu Awano; Hirofttmi Shimizu; Hiroshi Tsutsui; Hiroyuki Ochi (ISQED, 2012)

Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method. - Hiromitsu Awano; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Multi-trap RTN parameter extraction based on Bayesian inference. - Hiromitsu Awano; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ISQED, 2013)

Variability in device degradations: Statistical observation of NBTI for 3996 transistors. - Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ESSDERC, 2014)

Automation of Model Parameter Estimation for Random Telegraph Noise. - Hirofumi Shimizu; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Recognition of In-Field Frog Chorusing Using Bayesian Nonparametric Microphone Array Processing. - Yoshiaki Bando; Takuma Otsuka; Ikkyu Aihara; Hiromitsu Awano; Katsutoshi Itoyama; Kazuyoshi Yoshii; Hiroshi Gitchang Okuno (AAAI Workshop: Computational Sustainability, 2015)

ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell. - Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (DATE, 2015)

Efficient transistor-level timing yield estimation via line sampling. - Hiromitsu Awano; Takashi Sato 001 (DAC, 2016)

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. - Song Bian 001; Michihiro Shintani; Shumpei Morita; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ACM Great Lakes Symposium on VLSI, 2016)

Call Alternation Between Specific Pairs of Male Frogs Revealed by a Sound-Imaging Method in Their Natural Habitat. - Ikkyu Aihara; Takeshi Mizumoto; Hiromitsu Awano; Hiroshi G. Okuno (INTERSPEECH, 2016)

Physically unclonable function using RTN-induced delay fluctuation in ring oscillators. - Motoki Yoshinaga; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ISCAS, 2016)

Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling. - Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Variability in BTI-Induced Device Degradation: from Silicon Measurement to SRAM Yield Prediction. - Hiromitsu Awano (2016)

Efficient circuit failure probability calculation along product lifetime considering device aging. - Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ASP-DAC, 2017)

Yield Enhancement by Repair Circuits for Ultra-Fine Pitch Stacked-Chip Connections. - Keitaro Koga; Hiromitsu Awano; Makoto Ikeda (ATS, 2017)

Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation. - Hiromitsu Awano; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Identification and Application of Invariant Critical Paths under NBTI Degradation. - Song Bian 001; Shumpei Morita; Michihiro Shintani; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Swarm of Sound-to-Light Conversion Devices to Monitor Acoustic Communication Among Small Nocturnal Animals. - Takeshi Mizumoto; Ikkyu Aihara; Takuma Otsuka; Hiromitsu Awano; Hiroshi G. Okuno (J. Robotics Mechatronics, 2017)

Scalable Device Array for Statistical Characterization of BTI-Related Parameters. - Hiromitsu Awano; Shumpei Morita; Takashi Sato 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

RTN in Scaled Transistors for On-Chip Random Seed Generation. - Abinash Mohanty; Ketul B. Sutaria; Hiromitsu Awano; Takashi Sato 001; Yu Cao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An Encryption-Authentication Unified A/D Conversion Scheme for IoT Sensor Nodes. - Vinod V. Gadde; Hiromitsu Awano; Makoto Ikeda (A-SSCC, 2018)

31.3 μs/Signature-Generation 256-bit 픽p ECDSA Cryptoprocessor. - Shotaro Sugiyama; Hiromitsu Awano; Makoto Ikeda (A-SSCC, 2018)

Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFs. - Hiromitsu Awano; Takashi Sato 001 (DATE, 2018)

Low Latency 256-bit $mathbb{F}_p$ ECDSA Signature Generation Crypto Processor. - Shotaro Sugiyama; Hiromitsu Awano; Makoto Ikeda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

High-Speed ASIC Implementation of Paillier Cryptosystem with Homomorphism. - Chun Cai; Hiromitsu Awano; Makoto Ikeda (ASICON, 2019)

33us, 94uJ Optimal Ate Pairing Engine on BN Curve over 254b Prime Field in 65nm CMOS FDSOI. - Makoto Ikeda; Tadayuki Ichihashi; Hiromitsu Awano (A-SSCC, 2019)

Fourℚ on ASIC: Breaking Speed Records for Elliptic Curve Scalar Multiplication. - Hiromitsu Awano; Makoto Ikeda (DATE, 2019)

PUFNet: A Deep Neural Network Based Modeling Attack for Physically Unclonable Function. - Hiromitsu Awano; Tomoki Iizuka; Makoto Ikeda (ISCAS, 2019)

An ASIC Crypto Processor for 254-Bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field. - Hiromitsu Awano; Tadayuki Ichihashi; Makoto Ikeda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA. - Hiromitsu Awano; Masanori Hashimoto (DATE, 2020)

Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping. - Yasuhiro Ogasahara; Yohei Hori; Toshihiro Katashita; Tomoki Iizuka; Hiromitsu Awano; Makoto Ikeda; Hanpei Koike (Integr., 2020)

BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter. - Dehua Liang; Masanori Hashimoto; Hiromitsu Awano (DATE, 2021)

Binary Neural Network in Robotic Manipulation: Flexible Object Manipulation for Humanoid Robot Using Partially Binarized Auto-Encoder on FPGA. - Satoshi Ohara; Tetsuya Ogata; Hiromitsu Awano (IROS, 2021)

DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification. - Dehua Liang; Jun Shiomi; Noriyuki Miura; Hiromitsu Awano (ASP-DAC, 2022)

Respiratory Rate Estimation Based on WiFi Frame Capture. - Takamochi Kanda; Takashi Sato 001; Hiromitsu Awano; Sota Kondo; Koji Yamamoto 001 (CCNC, 2022)

Pay Attention via Binarization: Enhancing Explainability of Neural Networks via Binarization of Activation. - Yuma Tashiro; Hiromitsu Awano (ISCAS, 2022)

Temporal Ensemble SSDLite: Exploiting Temporal Correlation in Video for Accurate Object Detection. - Lukas Nakamura; Hiromitsu Awano (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter. - Dehua Liang; Jun Shiomi; Noriyuki Miura; Masanori Hashimoto; Hiromitsu Awano (IEICE Trans. Inf. Syst., 2022)

Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification. - Sosei Ikeda; Hiromitsu Awano; Takashi Sato 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits. - Dehua Liang; Hiromitsu Awano; Noriyuki Miura; Jun Shiomi (ASP-DAC, 2023)

Pay Attention via Quantization: Enhancing Explainability of Neural Networks via Quantized Activation. - Yuma Tashiro; Hiromitsu Awano (IEEE Access, 2023)

B2N2: Resource efficient Bayesian neural network accelerator using Bernoulli sampler on FPGA. - Hiromitsu Awano; Masanori Hashimoto (Integr., 2023)

BayesianPUFNet: Training Sample Efficient Modeling Attack for Physically Unclonable Functions. - Hiromitsu Awano; Makoto Ikeda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Uncertainty-Aware Haptic Shared Control With Humanoid Robots for Flexible Object Manipulation. - Takumi Hara; Takashi Sato 001; Tetsuya Ogata; Hiromitsu Awano (IEEE Robotics Autom. Lett., 2023)

Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility. - Sosei Ikeda; Hiromitsu Awano; Takashi Sato 001 (ACM Trans. Embed. Comput. Syst., 2023)

Triplet Network-Based DNA Encoding for Enhanced Similarity Image Retrieval. - Takefumi Koike; Hiromitsu Awano; Takashi Sato 001 (DAC, 2024)

Fast Parameter Optimization of Delayed Feedback Reservoir with Backpropagation and Gradient Descent. - Sosei Ikeda; Hiromitsu Awano; Takashi Sato 001 (DATE, 2024)

DNA-Based Similar Image Retrieval via Triplet Network-Driven Encoder. - Takefumi Koike; Hiromitsu Awano; Takashi Sato 001 (DATE, 2024)

S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators. - Mingtao Zhang; Quan Cheng; Hiromitsu Awano; Longyang Lin; Masanori Hashimoto (ICCD, 2024)

Square-Wave Defined Pulse Generator for High Fidelity Gate Operation of Superconducting Qubits. - Ryosuke Matsuo; Kazuhisa Ogawa; Hidehisa Shiorni; Makoto Negoro; Ryutaco Ohira; Takefumi Miyoshi; Michihiro Shintani; Hiromitsu Awano; Takashi Sato 001; Jun Shiomi (QCE, 2024)

Exploring Surface Code Decoding via Cryo-CMOS for Fault-Tolerant Quantum Computers. - Ruotai Wang; Takashi Sato 001; Hiromitsu Awano (QCE, 2024)

StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification. - Dehua Liang; Jun Shiomi; Noriyuki Miura; Hiromitsu Awano (IEEE Open J. Circuits Syst., 2024)

Double MAC on a Cell: A 22-nm 8T-SRAM-Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline. - Hiroto Tagata; Takashi Sato 001; Hiromitsu Awano (IEEE Open J. Circuits Syst., 2024)

A Robust and Energy Efficient Hyperdimensional Computing System for Voltage-scaled Circuits. - Dehua Liang; Hiromitsu Awano; Noriyuki Miura; Jun Shiomi (ACM Trans. Embed. Comput. Syst., 2024)

Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K. - Takuma Kawakami; Takashi Sato 001; Hiromitsu Awano (ASP-DAC, 2025)

A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-on-Chip Towards In-Orbit Computing. - Quan Cheng; Qiufeng Li; Weirong Dong; Mingtao Zhang; Ruilin Zhang; Mingqiang Huang; Hao Yu 001; Yiyu Shi 001; Hiromitsu Awano; Takashi Sato 001; Longyang Lin; Masanori Hashimoto (CICC, 2025)

Zero-Aware Regularization for Energy-Efficient Inference on Akida Neuromorphic Processor. - Takehiro Habara; Takashi Sato 001; Hiromitsu Awano (ISCAS, 2025)

Gaitcloud: Leveraging Spatial-Temporal Information for Lidar-Base Gait Recognition With a True-3D Gait Representation. - Shaoxiong Zhang; Hiromitsu Awano; Takashi Sato 001 (WACV, 2025)

Online Training and Inference System on Edge FPGA Using Delayed Feedback Reservoir. - Sosei Ikeda; Hiromitsu Awano; Takashi Sato 001 (CoRR, 2025)

Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation. - Hiroto Tagata; Takashi Sato 001; Hiromitsu Awano (CoRR, 2025)

SOME: Symmetric One-Hot Matching Elector - A Lightweight Microsecond Decoder for Quantum Error Correction. - Xinyi Guo; Geguang Miao; Shinichi Nishizawa; Hiromitsu Awano; Shinji Kimura; Takashi Sato 001 (CoRR, 2025)