Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline. - Kisaburo Nakazawa; Hiroshi Nakamura; Hiromitsu Imori; Shun Kawabe (SC, 1992)

A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers. - Hiroshi Nakamura; Taisuke Boku; Hideo Wada; Hiromitsu Imori; Ikuo Nakata; Yasuhiro Inagami; Kisaburo Nakazawa; Yoshiyuki Yamashita (International Conference on Supercomputing, 1993)

Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers. - Hiroshi Nakamura; Kisaburo Nakazawa; Hang Li; Hiromitsu Imori; Taisuke Boku; Ikuo Nakata; Yoshiyuki Yamashita (HICSS (1), 1994)