A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier. - Hisakazu Kotani; Hironori Akamatsu; Junko Matsushima; Shozo Okada; Tsuyoshi Shiragasawa; Takayoshi Yamada; Michihiro Inoue (IEEE J. Solid State Circuits, 1990)

A 256-Mb DRAM with 100 MHz serial I/O ports for storage of moving pictures. - Hisakazu Kotani; Hironori Akamatsu; Yasushi Naito; Toyokazu Fujii; Tohru Iwata; Toshiaki Tsuji; Yutaka Itoh; Norisato Shimizu; Junji Hirase; Yoshiyuki Shibata; Kazuhiro Yamashita; Takashi Hori; et al. (IEEE J. Solid State Circuits, 1994)

An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's. - Hiroyuki Yamauchi; Hironori Akamatsu; Tsutomu Fujita (IEEE J. Solid State Circuits, 1995)

A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. - Hiroyuki Yamauchi; Toru Iwata; Hironori Akamatsu; Akira Matsuzawa (ISLPED, 1996)

A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. - Hiroyuki Yamauchi; Toru Iwata; Hironori Akamatsu; Akira Matsuzawa (IEEE Trans. Very Large Scale Integr. Syst., 1997)

0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. - Toshikazu Suzuki; Yoshinobu Yamagami; Ichiro Hatanaka; Akinori Shibayama; Hironori Akamatsu; Hiroyuki Yamauchi (IEICE Trans. Electron., 2005)

A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. - Toshikazu Suzuki; Yoshinobu Yamagami; Ichiro Hatanaka; Akinori Shibayama; Hironori Akamatsu; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2006)

A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme. - Toshikazu Suzuki; Hiroyuki Yamauchi; Katsuji Satomi; Hironori Akamatsu (CICC, 2007)

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. - Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (ISSCC, 2007)

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. - Satoshi Ishikura; Marefusa Kurumada; Toshio Terano; Yoshinobu Yamagami; Naoki Kotani; Katsuji Satomi; Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Toshiyuki Oashi; Hiroshi Makino; et al. (IEEE J. Solid State Circuits, 2008)

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. - Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (IEEE J. Solid State Circuits, 2008)

A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses. - Toshikazu Suzuki; Hiroyuki Yamauchi; Yoshinobu Yamagami; Katsuji Satomi; Hironori Akamatsu (IEEE J. Solid State Circuits, 2008)