A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure. - Akira Umezawa; Shigeru Atsumi; Masao Kuriyama; Hironori Banba; Ken-ichi Imamiya; Kiyomi Naruke; Seiji Yamada; Etsushi Obi; Masamitsu Oshikiri; Tomoko Suzuki; Sumio Tanaka (IEEE J. Solid State Circuits, 1992)

A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation. - Shigeru Atsumi; Masao Kuriyama; Akira Umezawa; Hironori Banba; Kiyomi Naruke; Seiji Yamada; Yoichi Ohshima; Masamitsu Oshikiri; Yohei Hiura; Tomoko Yamane; Kuniyoshi Yoshikawa (IEEE J. Solid State Circuits, 1994)

A CMOS bandgap reference circuit with sub-1-V operation. - Hironori Banba; Hitoshi Shiga; Akira Umezawa; Takeshi Miyaba; Toru Tanzawa; Shigeru Atsumi; Koji Sakui (IEEE J. Solid State Circuits, 1999)

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus. - Toshimasa Namekawa; Shinji Miyano; Ryo Fukuda; Ryo Haga; Osamu Wada; Hironori Banba; Satoru Takeda; Kazuhiro Suda; Kenichiro Mimoto; Satoshi Yamaguchi; Tsutomu Ohkubo; Hiroshi Takato; et al. (IEEE J. Solid State Circuits, 2000)

Wordline voltage generating system for low-power low-voltage flash memories. - Toru Tanzawa; Akira Umezawa; Masao Kuriyama; Tadayuki Taura; Hironori Banba; Takeshi Miyaba; Hitoshi Shiga; Yoshinori Takano; Shigeru Atsumi (IEEE J. Solid State Circuits, 2001)