A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. - Takeshi Hamamoto; Kiyohiro Furutani; Takashi Kubo; Satoshi Kawasaki; Hironori Iga; Takashi Kono; Yasuhiro Konishi; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 2004)