Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing. - Hironori Kasahara; Seinosuke Narita (IEEE Trans. Computers, 1984)

Parallel processing of robot-arm control computation on a multimicroprocessor system. - Hironori Kasahara; Seinosuke Narita (IEEE J. Robotics Autom., 1985)

Parallel Processing of Robot Dynamics Simulation Using Optimal Multiprocessor Scheduling Algorithms. - Hironori Kasahara; Masahiko Iwata; Seinosuke Narita; Hirofumi Fujii (Syst. Comput. Jpn., 1988)

Application of df/ihs to minimum total weighted flow time multiprocessor scheduling problems. - Hironori Kasahara; Munenori Kai; Seinosuke Narita; Hidehiko Wada (Syst. Comput. Jpn., 1988)

A Compilation Scheme for Macro-Dataflow Computation on Hierarchical Multiprocessor Systems. - Hironori Kasahara; Hiroki Honda; Masahiko Iwata; M. Hirota (ICPP (2), 1990)

Parallel processing of near fine grain tasks using static scheduling OSCAR (optimally scheduled advanced multiprocessor). - Hironori Kasahara; Hiroki Honda; Seinosuke Narita (SC, 1990)

Parallel processing of robot arm dynamic control computation on multimicroprocessors. - Hironori Kasahara (Microprocess. Microsystems, 1990)

Parallel Processing of Sparse Matrix Solution Using Fine Grain Tasks on OSCAR. - Hironori Kasahara; Wichian Premchaiswadi; Mikio Tamura; Yoshinori Maekawa; Seinosuke Narita (ICPP (3), 1991)

A Multi-Grain Parallelizing Compilation Scheme for OSCAR (Optimally Scheduled Advanced Multiprocessor). - Hironori Kasahara; Hiroki Honda; A. Mogi; A. Ogura; K. Fujiwara; Seinosuke Narita (LCPC, 1991)

Coarse grain parallelism detection scheme of a fortran program. - Hiroki Honda; Hironori Kasahara (Syst. Comput. Jpn., 1991)

Parallel processing scheme of a basic block in a fortran program on oscar. - Hiroki Honda; Satoshi Mizuno; Hironori Kasahara; Seinosuke Narita (Syst. Comput. Jpn., 1991)

Parallel Processing of robot control and simulation. - Hironori Kasahara (Parallel Computation Systems for Robotics, 1992)

A parallel optimization algorithm for minimum execution-time multiprocessor scheduling problem. - Hironori Kasahara; Atsusi Itoh; Hisamitsu Tanaka; Keisuke Itoh (Syst. Comput. Jpn., 1992)

Data-Localization for Fortran Macro-Dataflow Computation Using Partial Static Task Assignment. - Akimasa Yoshida; Kenichi Koshizuka; Hironori Kasahara (International Conference on Supercomputing, 1996)

Data Localization Using Loop Aligned Decomposition for Macro-Dataflow Processing. - Akimasa Yoshida; Hironori Kasahara (LCPC, 1996)

Job Scheduling Scheme for Pure Space Sharing Among Rigid Jobs. - Kento Aida; Hironori Kasahara; Seinosuke Narita (JSSPP, 1998)

A Data-Localization Compilation Scheme Using Partial-Static Task Assignment for Fortran Coarse-Grain Parallel Processing. - Hironori Kasahara; Akimasa Yoshida (Parallel Comput., 1998)

Coarse-Grain Task Parallel Processing Using the OpenMP Backend of the OSCAR Multigrain Parallelizing Compiler. - Kazuhisa Ishizaka; Motoki Obata; Hironori Kasahara (ISHPC, 2000)

Automatic Coarse Grain Task Parallel Processing on SMP Using OpenMP. - Hironori Kasahara; Motoki Obata; Kazuhisa Ishizaka (LCPC, 2000)

Performance Evaluation of Minimum Execution Time Multiprocessor Scheduling Algorithms Using Standard Task Graph Set. - Takao Tobita; Masayoshi Kouda; Hironori Kasahara (PDPTA, 2000)

Coarse Grain Task Parallel Processing with Cache Optimization on Shared Memory Multiprocessor. - Kazuhisa Ishizaka; Motoki Obata; Hironori Kasahara (LCPC, 2001)

Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP. - Hirofumi Nakano; Kazuhisa Ishizaka; Motoki Obata; Keiji Kimura; Hironori Kasahara (ISHPC, 2002)

Hierarchical Parallelism Control for Multigrain Parallel Processing. - Motoki Obata; Jun Shirako; Hiroki Kaminaga; Kazuhisa Ishizaka; Hironori Kasahara (LCPC, 2002)

Multigrain Automatic Parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler. - Hironori Kasahara; Motoki Obata; Kazuhisa Ishizaka; Keiji Kimura; Hiroki Kaminaga; Hirofumi Nakano; Kouhei Nagasawa; Akiko Murai; Hiroki Itagaki; Jun Shirako (PARELEC, 2002)

Humanoid Robots in Waseda University-Hadaly-2 and WABIAN. - Shuji Hashimoto; Seinosuke Narita; Hironori Kasahara; Katsuhiko Shirai; Atsuo Kobayashi; Atsuo Takanishi; Shigeki Sugano; Jin'ichi Yamaguchi; Hideyuki Sawada; Hideaki Takanobu; Koji Shibuya; Toshio Morita; et al. (Auton. Robots, 2002)

Cache Optimization for Coarse Grain Task Parallel Processing Using Inter-Array Padding. - Kazuhisa Ishizaka; Motoki Obata; Hironori Kasahara (LCPC, 2003)

Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers. - Kazuhisa Ishizaka; Takamichi Miyamoto; Jun Shirako; Motoki Obata; Keiji Kimura; Hironori Kasahara (LCPC, 2004)

Selective inline expansion for improvement of multi grain parallelism. - Jun Shirako; Kouhei Nagasawa; Kazuhisa Ishizaka; Motoki Obata; Hironori Kasahara (Parallel and Distributed Computing and Networks, 2004)

Multigrain parallel processing on compiler cooperative chip multiprocessor. - Keiji Kimura; Yasutaka Wada; Hirofumi Nakano; Takeshi Kodaka; Jun Shirako; Kazuhisa Ishizaka; Hironori Kasahara (Interaction between Compilers and Computer Architectures, 2005)

Performance Evaluation of Compiler Controlled Power Saving Scheme. - Jun Shirako; Munehiro Yoshida; Naoto Oshiyama; Yasutaka Wada; Hirofumi Nakano; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (ISHPC, 2005)

Compiler Control Power Saving Scheme for Multi Core Processors. - Jun Shirako; Naoto Oshiyama; Yasutaka Wada; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (LCPC, 2005)

Power-Aware Compiler Controllable Chip Multiprocessor. - Hiroaki Shikano; Jun Shirako; Yasutaka Wada; Keiji Kimura; Hironori Kasahara (PACT, 2007)

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. - Yutaka Yoshida; Tatsuya Kamei; Kiyoshi Hayase; Shinichi Shibahara; Osamu Nishii; Toshihiro Hattori; Atsushi Hasegawa; Masashi Takada; Naohiko Irie; Kunio Uchiyama; Toshihiko Odaka; Kiwamu Takada; et al. (ISSCC, 2007)

Language Extensions in Support of Compiler Parallelization. - Jun Shirako; Hironori Kasahara; Vivek Sarkar (LCPC, 2007)

Software-cooperative power-efficient heterogeneous multi-core for media processing. - Hiroaki Shikano; Masaki Ito; Kunio Uchiyama; Toshihiko Odaka; Akihiro Hayashi; Takeshi Masuura; Masayoshi Mase; Jun Shirako; Yasutaka Wada; Keiji Kimura; Hironori Kasahara (ASP-DAC, 2008)

Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API. - Takamichi Miyamoto; Saori Asaka; Hiroki Mikami; Masayoshi Mase; Yasutaka Wada; Hirofumi Nakano; Keiji Kimura; Hironori Kasahara (ISPA, 2008)

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. - Masayuki Ito; Toshihiro Hattori; Yutaka Yoshida; Kiyoshi Hayase; Tomoichi Hayashi; Osamu Nishii; Yoshihiko Yasu; Atsushi Hasegawa; Masashi Takada; Hiroyuki Mizuno; Kunio Uchiyama; Toshihiko Odaka; et al. (ISSCC, 2008)

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. - Hiroaki Shikano; Masaki Ito; Masafumi Onouchi; Takashi Todaka; Takanobu Tsunoda; Tomoyuki Kodama; Kunio Uchiyama; Toshihiko Odaka; Tatsuya Kamei; Ei Nagahama; Manabu Kusaoke; Yusuke Nitta; et al. (IEEE J. Solid State Circuits, 2008)

Multiple-Paths Search with Concurrent Thread Scheduling for Fast AND/OR Tree Search. - Fumiyo Takano; Yoshitaka Maekawa; Hironori Kasahara (CISIS, 2009)

Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. - Masafumi Onouchi; Keisuke Toyama 003; Tohru Nojiri; Makoto Sato; Masayoshi Mase; Jun Shirako; Mikiko Sato; Masashi Takada; Masayuki Ito; Hiroyuki Mizuno; Mitaro Namiki; Keiji Kimura; et al. (ICPP, 2009)

OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers. - Keiji Kimura; Masayoshi Mase; Hiroki Mikami; Takamichi Miyamoto; Jun Shirako; Hironori Kasahara (LCPC, 2009)

A 45nm 37.3GOPS/W heterogeneous multi-core SoC. - Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Shigezumi Matsui; Osamu Nishii; Atsushi Hasegawa; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Koichi Terada; Tohru Nojiri; et al. (ISSCC, 2010)

Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores. - Akihiro Hayashi; Yasutaka Wada; Takeshi Watanabe; Takeshi Sekiguchi; Masayoshi Mase; Jun Shirako; Keiji Kimura; Hironori Kasahara (LCPC, 2010)

Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-Power Multicore. - Hiroki Mikami; Shumpei Kitaki; Masayoshi Mase; Akihiro Hayashi; Mamoru Shimaoka; Keiji Kimura; Masato Edahiro; Hironori Kasahara (LCPC, 2011)

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. - Osamu Nishii; Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Yasutaka Wada; Keiji Kimura; Hironori Kasahara; Hideo Maejima (IEICE Trans. Electron., 2011)

A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture. - Yasutaka Wada; Akihiro Hayashi; Takeshi Masuura; Jun Shirako; Hirofumi Nakano; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (Trans. High Perform. Embed. Archit. Compil., 2011)

Enhancing the performance of a multiplayer game by using a parallelizing compiler. - Yasir I. M. Al-Dosary; Keiji Kimura; Hironori Kasahara; Seinosuke Narita (CGAMES, 2012)

Automatic parallelization, performance predictability and power control for mobile-applications. - Dominic Hillenbrand; Akihiro Hayashi; Hideo Yamamoto; Keiji Kimura; Hironori Kasahara (COOL Chips, 2013)

Parallelization of automotive engine control software on embedded multi-core processor using OSCAR compiler. - Yohei Kanehagi; Dan Umeda; Akihiro Hayashi; Keiji Kimura; Hironori Kasahara (COOL Chips, 2013)

Dynamic Profiling and Feedback Framework for Reduce-Side Join. - Makoto Nakayama; Kenichi Yamazaki; Satoshi Tanaka; Hironori Kasahara (CSE, 2013)

OSCAR Compiler Controlled Multicore Power Reduction on Android Platform. - Hideo Yamamoto; Tomohiro Hirano; Kohei Muto; Hiroki Mikami; Takashi Goto 003; Dominic Hillenbrand; Moriyuki Takamura; Keiji Kimura; Hironori Kasahara (LCPC, 2013)

Reconciling application power control and operating systems for optimal power and performance. - Dominic Hillenbrand; Yuuki Furuyama; Akihiro Hayashi; Hiroki Mikami; Keiji Kimura; Hironori Kasahara (ReCoSoC, 2013)

Parallelization of tree-to-TLV serialization. - Makoto Nakayama; Kenichi Yamazaki; Satoshi Tanaka; Hironori Kasahara (IPCCC, 2014)

Evaluation of Automatic Power Reduction with OSCAR Compiler on Intel Haswell and ARM Cortex-A9 Multicores. - Tomohiro Hirano; Hideo Yamamoto; Shuhei Iizuka; Kohei Muto; Takashi Goto 003; Tamami Wake; Hiroki Mikami; Moriyuki Takamura; Keiji Kimura; Hironori Kasahara (LCPC, 2014)

Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various Cc-NUMA Servers. - Mamoru Shimaoka; Yasutaka Wada; Keiji Kimura; Hironori Kasahara (LCPC, 2015)

Multigrain Parallelization for Model-Based Design Applications Using the OSCAR Compiler. - Dan Umeda; Takahiro Suzuki; Hiroki Mikami; Keiji Kimura; Hironori Kasahara (LCPC, 2015)

Annotatable systrace: an extended Linux ftrace for tracing a parallelized program. - Daichi Fukui; Mamoru Shimaoka; Hiroki Mikami; Dominic Hillenbrand; Hideo Yamamoto; Keiji Kimura; Hironori Kasahara (SEPS@SPLASH, 2015)

What Will 2022 Look Like? The IEEE CS 2022 Report. - Hasan Alkhatib; Paolo Faraboschi; Eitan Frachtenberg; Hironori Kasahara; Danny B. Lange; Phillip A. Laplante; Arif Merchant; Dejan S. Milojicic; Karsten Schwan (Computer, 2015)

Automatic Local Memory Management for Multicores Having Global Address Space. - Kouhei Yamamoto; Tomoya Shirakawa; Yoshitake Oki; Akimasa Yoshida; Keiji Kimura; Hironori Kasahara (LCPC, 2016)

Accelerating Multicore Architecture Simulation Using Application Profile. - Keiji Kimura; Gakuho Taguchi; Hironori Kasahara (MCSoC, 2016)

Architecture Design for the Environmental Monitoring System over the Winter Season. - Koichiro Yamashita; Takahisa Suzuki; Hongchun Li; Chen Ao; Yi Xu 020; Jun Tian; Keiji Kimura; Hironori Kasahara (MobiWac, 2016)

Reducing parallelizing compilation time by removing redundant analysis. - Jixin Han; Rina Fujino; Ryota Tamura; Mamoru Shimaoka; Hiroki Mikami; Moriyuki Takamura; Sachio Kamiya; Kazuhiko Suzuki; Takahiro Miyajima; Keiji Kimura; Hironori Kasahara (SEPS@SPLASH, 2016)

Android Video Processing System Combined with Automatically Parallelized and Power Optimized Code by OSCAR Compiler. - Bui Duc Binh; Tomohiro Hirano; Hiroki Mikami; Hideo Yamamoto; Keiji Kimura; Hironori Kasahara (J. Inf. Process., 2016)

Multicore Cache Coherence Control by a Parallelizing Compiler. - Hironori Kasahara; Keiji Kimura; Boma A. Adhi; Yuhei Hosokawa; Yohei Kishimoto; Masayoshi Mase (COMPSAC (1), 2017)

Message from the CAP 2017 Organizing Committee. - Cristina Seceleanu; Hironori Kasahara; Tiberiu Seceleanu (COMPSAC (1), 2017)

Panel discussions: "Cool chips for the next decade". - Hideharu Amano; Tadao Nakamura; Hiroaki Kobayashi; Hironori Kasahara; Yoshiaki Hagiwara; Jeffrey L. Burns; David Brash (COOL Chips, 2017)

Software Cache Coherent Control by Parallelizing Compiler. - Boma A. Adhi; Masayoshi Mase; Yuhei Hosokawa; Yohei Kishimoto; Taisuke Onishi; Hiroki Mikami; Keiji Kimura; Hironori Kasahara (LCPC, 2017)

Satisfaction and Sustainability. - Hironori Kasahara (Computer, 2018)

Fast and Highly Optimizing Separate Compilation for Automatic Parallelization. - Tohma Kawasumi; Ryota Tamura; Yuya Asada; Jixin Han; Hiroki Mikami; Keiji Kimura; Hironori Kasahara (HPCS, 2019)

Performance of Static and Dynamic Task Scheduling for Real-Time Engine Control System on Embedded Multicore Processor. - Yoshitake Oki; Hiroki Mikami; Hikaru Nishida; Dan Umeda; Keiji Kimura; Hironori Kasahara (LCPC, 2019)

Cascaded DMA Controller for Speedup of Indirect Memory Access in Irregular Applications. - Tomoya Kashimata; Toshiaki Kitamura; Keiji Kimura; Hironori Kasahara (IA3@SC, 2019)

Collaboration for the Future. - Hironori Kasahara (Computer, 2019)

Guest Editorial: Special Issue on Network and Parallel Computing for Emerging Architectures and Applications. - Feng Zhang 007; Jidong Zhai; Marc Snir; Hai Jin 001; Hironori Kasahara; Mateo Valero (Int. J. Parallel Program., 2019)

Computer Education in the Age of COVID-19. - Jean-Luc Gaudiot; Hironori Kasahara (Computer, 2020)

Compiler Software Coherent Control for Embedded High Performance Multicore. - Boma A. Adhi; Tomoya Kashimata; Ken Takahashi; Keiji Kimura; Hironori Kasahara (IEICE Trans. Electron., 2020)

Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler. - Yoshitake Oki; Yuto Abe; Kazuki Yamamoto; Kohei Yamamoto; Tomoya Shirakawa; Akimasa Yoshida; Keiji Kimura; Hironori Kasahara (IEICE Trans. Electron., 2020)

Parallelizing Compiler Translation Validation Using Happens-Before and Task-Set. - Jixin Han; Tomofumi Yuki; Michelle Mills Strout; Dan Umeda; Hironori Kasahara; Keiji Kimura (CANDAR (Workshops), 2021)

Performance Evaluation of OSCAR Multi-target Automatic Parallelizing Compiler on Intel, AMD, Arm and RISC-V Multicores. - Birk Martin Magnussen; Tohma Kawasumi; Hiroki Mikami; Keiji Kimura; Hironori Kasahara (LCPC, 2021)

OSCAR Parallelizing and Power Reducing Compiler and API for Heterogeneous Multicores : (Invited Paper). - Hironori Kasahara; Keiji Kimura; Toshiaki Kitamura; Hiroki Mikami; Kazutaka Morita; Kazuki Fujita; Kazuki Yamamoto; Tohma Kawasumi (PEHC@SC, 2021)

Engineering Education in the Age of Autonomous Machines. - Shaoshan Liu; Jean-Luc Gaudiot; Hironori Kasahara (Computer, 2021)

Parallelizing Factory Automation Ladder Programs by OSCAR Automatic Parallelizing Compiler. - Tohma Kawasumi; Yuta Tsumura; Hiroki Mikami; Tomoya Yoshikawa; Takero Hosomi; Shingo Oidate; Keiji Kimura; Hironori Kasahara (LCPC, 2022)

The Invention of Electronic Digital Computing - Plenary Panel Summary. - John Vincent Atanasoff; Gordon Bell; Kiril L. Boyanov; Charles G. Call; Carl K. Chang; Thomas M. Conte; Vladimir Getov; John L. Gustafson; Hironori Kasahara; Dejan S. Milojicic; Michael R. Williams (JVA, 2023)

Automatic Deep Learning Parallelization for Vector Multicore Chips with the OSCAR Parallelizing and the TVM Open-Source Deep Learning Compiler. - Fumiaki Onishi; Ryosei Otaka; Kazuki Fujita; Tomoki Suetsugu; Tohma Kawasumi; Toshiaki Kitamura; Hironori Kasahara; Keiji Kimura (LCPC, 2023)