Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations. - Kei Hiraki; Hideharu Amano; Morihiro Kuga; Toshinori Sueyoshi; Tomohiro Kudoh; Hiroshi Nakashima; Hironori Nakajo; Hideo Matsuda; Takashi Matsumoto 002; Shin-ichiro Mori (ISPAN, 1994)

High Performance I/O System of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. - Hironori Nakajo; Takashi Matsumoto 002; Masaki Kohata; Hideo Matsuda; Kei Hiraki; Yukio Kaneda (Parallel and Distributed Computing and Systems, 1995)

A Simulation-based Evaluation of a Disk I/O Subsystem for a Massively Parallel Computer: JUMP-1. - Hironori Nakajo; Satoshi Ohtani; Yukio Kaneda (ICDCS, 1996)

An I/O Network Architecture of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. - Hironori Nakajo; Satoshi Ohtani; Takashi Matsumoto 002; Masadi Kohata; Kei Hiraki; Yukio Kaneda (International Conference on Supercomputing, 1997)

An Implementation and Evaluation of a Distributed Shared-Memory System on Workstation Clusters Using Fast Serial Links. - Hironori Nakajo; Akihiro Ichikawa; Yukio Kaneda (ISHPC, 1997)

Distributed Shared-Memory for a Workstation Cluster with a High Speed Serial Interface. - Hironori Nakajo; Hidekazu Tanaka; Yoshinori Nakanishi; Masaki Kohata; Yukio Kaneda (HPCN Europe, 1998)

MEMOnet : Network interface plugged into a memory slot. - Noboru Tanabe; Junji Yamamoto; Hiroaki Nishi; Tomohiro Kudoh; Yoshihiro Hamada; Hironori Nakajo; Hideharu Amano (CLUSTER, 2000)

On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. - Noboru Tanabe; Junji Yamamoto; Hiroaki Nishi; Tomohiro Kudoh; Yoshihiro Hamada; Hironori Nakajo; Hideharu Amano (ISPAN, 2000)

Coherence Protocol for Home Proxy Cache on RHiNET. - Hironori Nakajo; M. Ishii; T. Kudo; Hideharu Amano (PDPTA, 2000)

A Distributed Shared-Memory System on a Workstation Cluster Using Fast Serial Links. - Hironori Nakajo; Akihiro Ichikawa; Yukio Kaneda (Int. J. Parallel Program., 2000)

Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. - Noboru Tanabe; Yoshihiro Hamada; Hironori Nakajo; Hideki Imashiro; Junji Yamamoto; Tomohiro Kudoh; Hideharu Amano (PARELEC, 2002)

Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. - Noboru Tanabe; Junji Yamamoto; Hiroaki Nishi; Tomohiro Kudoh; Yoshihiro Hamada; Hironori Nakajo; Hideharu Amano (Clust. Comput., 2002)

Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. - Hironori Nakajo; Masanori Yamato; Shoji Kawahara; Norito Kato; Koichi Sasada; Mikiko Sato; Mitaro Namiki (PDPTA, 2003)

Implementation and Evaluation of a Thread Library for Multithreaded Architecture. - Koichi Sasada; Mikiko Sato; Shoji Kawahara; Norito Kato; Masanori Yamato; Hironori Nakajo; Mitaro Namiki (PDPTA, 2003)

A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. - Mikiko Sato; Koichi Sasada; Shoji Kawahara; Norito Kato; Masanori Yamato; Hironori Nakajo; Mitaro Namiki (PDPTA, 2003)

A New Memory Module for Memory Intensive Applications. - Noboru Tanabe; Hironori Nakajo; Hirotaka Hakozaki; Masasige Nakatake; Yasunori Dohi; Hideharu Amano (PARELEC, 2004)

Dynamic Allocation of Physical Register Banks for an SMT Processor. - Norito Kato; Masanori Yamato; Osamu Tujimoto; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Mitaro Namiki; Hironori Nakajo (PDPTA, 2004)

Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. - Yasuo Miyabe; Akira Kitamura; Yoshihiro Hamada; Tomotaka Miyashiro; Tetsu Izawa; Noboru Tanabe; Hironori Nakajo; Hideharu Amano (ISHPC, 2005)

Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. - Akira Kitamura; Yasuo Miyabe; Tetsu Izawa; Tomotaka Miyashiro; Konosuke Watanabe; Tomohiro Otsuka; Hideharu Amano; Yoshihiro Hamada; Noboru Tanabe; Hironori Nakajo (PDCAT, 2005)

A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. - Yoshihiro Hamada; Hiroaki Nishi; Akira Kitamura; Noboru Tanabe; Hideharu Amano; Hironori Nakajo (PDPTA, 2005)

A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. - Yoshiyasu Ogasawara; Norito Kato; Masanori Yamato; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Mitaro Namiki; Hironori Nakajo (PDPTA, 2005)

Development of a Thread Scheduler for SMT Processor Architecture. - Kaname Uchikura; Koichi Sasada; Mikiko Sato; Masanori Yamato; Norito Kato; Hironori Nakajo; Mitaro Namiki (PDPTA, 2005)

DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. - Tomotaka Miyashiro; Akira Kitamura; Hironori Nakajo; Noboru Tanabe (FPL, 2006)

Implementation of PC Cluster System with Memory Mapped File by Commodity OS. - Jun Kanai; Takuro Mori; Takeshi Araki; Noboru Tanabe; Hironori Nakajo; Mitaro Namiki (PDPTA, 2006)

Towards Reconfigurable Cache Memory for a Multithreaded Processor. - Yoshiyasu Ogasawara; Ippei Tate; Satoshi Watanabe; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Kazunari Asano; Mitaro Namiki; Hironori Nakajo (PDPTA, 2006)

A Model of Implementable SMT Processor on FPGA. - Ippei Tate; Yoshiyasu Ogasawara; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Kazunari Asano; Satoshi Watanabe; Mitaro Namiki; Hironori Nakajo (PDPTA, 2006)

Performance evaluation on low-latency communication mechanism of DIMMnet-2. - Akira Kitamura; Yasuo Miyabe; Tomotaka Miyashiro; Noboru Tanabe; Hironori Nakajo; Hideharu Amano (Parallel and Distributed Computing and Networks, 2007)

Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. - Atsushi Ohta; Yoshihiro Hamada; Akira Kitamura; Noboru Tanabe; Hideharu Amano; Hironori Nakajo (PDPTA, 2007)

Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices. - Satoshi Watanabe; Yoshiyasu Ogasawara; Ippei Tate; Hirofumi Yano; Hironori Nakajo (PDPTA, 2007)

Introduction. - Kenji Kise; Toshinori Sato; Hironori Nakajo (SIGARCH Comput. Archit. News, 2007)

Low-Complexity Bypass Network Using Small RAM. - Shinobu Miwa; Hironori Ichibayashi; Hidetsugu Irie; Masahiro Goshima; Hironori Nakajo; Shinji Tomita (CDES, 2008)

An Enhancer of Memory and Network for Cluster and its Applications. - Noboru Tanabe; Hironori Nakajo (PDCAT, 2008)

Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network. - Noboru Tanabe; Hironori Nakajo (PVM/MPI, 2008)

Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor. - Yoshiyasu Ogasawara; Pulung Waskito; Shinobu Miwa; Hironori Nakajo (CDES, 2009)

An Effective Replacement Strategy of Cache Memory for an SMT Processor. - Yoshiyasu Ogasawara; Hironori Nakajo (DSD, 2009)

Network Interface Architecture for Scalable Message Queue Processing. - Noboru Tanabe; Atsushi Ohta; Pulung Waskito; Hironori Nakajo (ICPADS, 2009)

The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing. - Noboru Tanabe; Manami Sasaki; Hironori Nakajo; Masami Takata; Kazuki Joe (PDPTA, 2009)

An Effective Replacement Policy Focusing on Lifetime of a Cache Line. - Hiroki Yokoyama; Yuhei Horibe; Peng Zhang; Shinobu Miwa; Hironori Nakajo (CDES, 2010)

Parallelizing Hilbert-Huang Transform on a GPU. - Pulung Waskito; Shinobu Miwa; Yasue Mitsukura; Hironori Nakajo (ICNC, 2010)

Acceleration for MPI derived datatypes using an enhancer of memory and network. - Noboru Tanabe; Hironori Nakajo (IPDPS Workshops, 2010)

An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing. - Noboru Tanabe; Hirotaka Hakozaki; Hiroshi Ando; Yasunori Dohi; Zhengzhe Luo; Hironori Nakajo (J. Supercomput., 2010)

Detecting water waste activities for water-efficient living. - Trang Thuy Vu; Akifumi Sokan; Hironori Nakajo; Kaori Fujinami; Jaakko Suutala; Pekka Siirtola; Tuomo Alasalmi; Ari Pitkänen; Juha Röning (UbiComp, 2011)

Reconfigurable Android with an FPGA Accelerator for the Future Embedded Devices. - Hironori Nakajo; Keisuke Koike; Atsushi Ohta; Kohta Ohshima; Kaori Fujinami (ICNC, 2011)

Feature Selection and Activity Recognition to Detect Water Waste from Water Tap Usage. - Trang Thuy Vu; Akifumi Sokan; Hironori Nakajo; Kaori Fujinami; Jaakko Suutala; Pekka Siirtola; Tuomo Alasalmi; Ari Pitkänen; Juha Röning (RTCSA (2), 2011)

A memory accelerator with gather functions for bandwidth-bound irregular applications. - Noboru Tanabe; Boonyasitpichai Nuttapon; Hironori Nakajo; Yuka Ogawa; Junko Kogou; Masami Takata; Kazuki Joe (IA3@SC, 2011)

Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis. - Pulung Waskito; Shinobu Miwa; Yasue Mitsukura; Hironori Nakajo (IEICE Trans. Inf. Syst., 2011)

Design of real-time advanced lens free imager. - Masashi Takemoto; Ryota Suzuki 004; Katsuhiko Umeno; Masayuki Yashiro; Tetsuya Ryuchi; Kohta Ohshima; Naoya Kitagawa; Hironori Nakajo (SoICT, 2016)

Performance evaluation of an SoC for the real-time lens-free imager RALFIE. - Masashi Takemoto; Ryota Suzuki 004; Katsuhiko Umeno; Masayuki Yashiro; Tetsuya Ryuchi; Kohta Ohshima; Naoya Kitagawa; Hironori Nakajo (GCCE, 2017)

Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool. - Yuto Ishikawa; Keitaro Yanai; Keisuke Koike; Takefumi Miyoshi; Hironori Nakajo (HEART, 2017)

Implementation of DNN on a RISC-V Open Source Microprocessor for IoT devices. - Jingyong Cai; Masashi Takemoto; Hironori Nakajo (GCCE, 2018)

A Deep Look into Logarithmic Quantization of Model Parameters in Neural Networks. - Jingyong Cai; Masashi Takemoto; Hironori Nakajo (IAIT, 2018)

Operation in Partitioned Circuits with Scalable Hardware Mechanism. - Yusuke Katoh; Hironari Yoshiuchi; Yoshio Murata; Hironori Nakajo (JCSSE, 2018)

Cow estrus detection via Discrete Wavelet Transformation and Unsupervised Clustering. - Le Tien Thanh 001; Rin Nishikawa; Masashi Takemoto; Huynh Thi Thanh Binh; Hironori Nakajo (SoICT, 2018)

Fault-tolerant Routing based on Routing Capabilities in a Hyper-Star Graph. - Yo Nishiyama; Yuko Sasaki; Yuki Hirai; Hironori Nakajo; Keiichi Kaneko (J. Inf. Sci. Eng., 2018)

Interactive Cultivation System for the Future IoT-Based Agriculture. - Kesevan Veloo; Hayate Kojima; Shogo Takata; Masashi Nakamura; Hironori Nakajo (CANDAR Workshops, 2019)

Parallelization of Recursive Function in Ruby-Based High-Level Synthesis. - Ryota Yamashita; Daichi Teruya; Hironori Nakajo (FPT, 2019)

Cow estrus detection with low-frequency accelerometer sensor by unsupervised learning. - Tran Viet Toan; Rin Nishikawa; Le Tien Thanh 001; Masashi Takemoto; Tran Van Hoai; Huynh Thi Thanh Binh; Hironori Nakajo (SoICT, 2019)

A Ruby-Based Hardware/Software Co-Design Environment with Functional Reactive Programming: Mulvery. - Daichi Teruya; Hironori Nakajo (IEICE Trans. Inf. Syst., 2020)

Editor's Message to Special Issue of Embedded Systems Engineering. - Hironori Nakajo (J. Inf. Process., 2021)

Implementation of a RISC-V SMT Core in an AI processor. - Hidetaro Tanaka; Tomoaki Tanaka; Ryosuke Higashi; Tsutomu Sekibe; Shuichi Takada; Hironori Nakajo (SoICT, 2022)

Matthiola incana classification using CNN and class activation maps for model understanding. - Kentaro Machida; Soma Asuka; Tomomi Osaka; Fumikazu Watanabe; Hironori Nakajo (CANDARW, 2024)

Weed Detection from the Duck's Perspective Using Aqua-Drone in Rice Paddies. - Soma Asuka; Kentaro Machida; Tetsuya Nakamura; Ikuko Shimizu; Taiichiro Ookawa; Hironori Nakajo (GCCE, 2024)

Learning Algorithm for LesserDNN, a DNN with Quantized Weights. - Masashi Takemoto; Yasutake Masuda; Jingyong Cai; Hironori Nakajo (Informatica (Slovenia), 2025)

Simulation environment for reconfigurable virtual accelerators using a field programmable gate array development environment. - Shunya Kawai; Eriko Maeda; Kazuki Yaguchi; Yasunori Osana; Takefumi Miyoshi; Hironori Nakajo (J. Supercomput., 2025)

Preliminary evaluation of SHAVER: sharing vector registers with an accelerator. - Tomoaki Tanaka; Michiya Kato; Yasunori Osana; Takefumi Miyoshi; Jubee Tada; Kiyofumi Tanaka; Hironori Nakajo (J. Supercomput., 2025)