Complexity-Reducing Algorithm for Serial Scheduled Min-Sum Decoding of LDPC Codes. - Hironori Uchikawa; Kohsuke Harada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Terminated LDPC convolutional codes over GF(2p). - Hironori Uchikawa; Kenta Kasai; Kohichi Sakaniwa (Allerton, 2010)

Terminated LDPC Convolutional Codes over GF(2^p) - Hironori Uchikawa; Kenta Kasai; Kohichi Sakaniwa (CoRR, 2010)

Optimum Soft-Output of Autoregressive Detector for Offtrack Interference in LDPC-Coded Perpendicular Magnetic Recording. - Kohsuke Harada; Haruka Obata; Hironori Uchikawa; Kenji Yoshida; Yuji Sakai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Spatially coupled LDPC codes for decode-and-forward in erasure relay channel. - Hironori Uchikawa; Kenta Kasai; Kohichi Sakaniwa (ISIT, 2011)

Spatially Coupled Protograph-Based LDPC Codes for Decode-and-Forward in Erasure Relay Channel. - Hironori Uchikawa; Kenta Kasai; Kohichi Sakaniwa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Design and Performance of Rate-Compatible Non-binary LDPC Convolutional Codes. - Hironori Uchikawa; Kenta Kasai; Kohichi Sakaniwa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Threshold improvement of low-density lattice codes via spatial coupling. - Hironori Uchikawa; Brian M. Kurkoski; Kenta Kasai; Kohichi Sakaniwa (ICNC, 2012)

Iterative encoding with Gauss-Seidel method for spatially-coupled low-density lattice codes. - Hironori Uchikawa; Brian M. Kurkoski; Kenta Kasai; Kohichi Sakaniwa (ISIT, 2012)

Design of non-precoded protograph-based LDPC codes. - Hironori Uchikawa (ISIT, 2014)

Error analysis and inter-cell interference mitigation in multi-level cell flash memories. - Veeresh Taranalli; Hironori Uchikawa; Paul H. Siegel (ICC, 2015)

Linear locally repairable codes with availability. - Pengfei Huang 001; Eitan Yaakobi; Hironori Uchikawa; Paul H. Siegel (ISIT, 2015)

Cyclic linear binary locally repairable codes. - Pengfei Huang 001; Eitan Yaakobi; Hironori Uchikawa; Paul H. Siegel (ITW, 2015)

Integrated parallel interleaved concatenation for lowering error floors of LDPC codes. - Naoaki Kokubun; Hironori Uchikawa (ISIT, 2016)

On the Capacity of the Beta-Binomial Channel Model for Multi-Level Cell Flash Memories. - Veeresh Taranalli; Hironori Uchikawa; Paul H. Siegel (IEEE J. Sel. Areas Commun., 2016)

Channel Models for Multi-Level Cell Flash Memories Based on Empirical Error Analysis. - Veeresh Taranalli; Hironori Uchikawa; Paul H. Siegel (IEEE Trans. Commun., 2016)

Binary Linear Locally Repairable Codes. - Pengfei Huang 001; Eitan Yaakobi; Hironori Uchikawa; Paul H. Siegel (IEEE Trans. Inf. Theory, 2016)

Complete Multipartite Graph Codes. - Yuta Kumano; Yoshiyuki Sakamaki; Hironori Uchikawa (ISITA, 2018)

Circuit-Size Reduction for Parallel Chien Search using Minimal Polynomial Degree Reduction. - Naoaki Kokubun; Akira Yamaga; Hironori Uchikawa; Daiki Watanabe (ISCAS, 2019)

Approximated EM Algorithms for Estimation of Unknown Coded Discrete Memoryless Channels. - Naoaki Kokubun; Daiki Watanabe; Hironori Uchikawa; Paul H. Siegel (GLOBECOM, 2020)

7-Bit/2Cell (X3.5), 9-Bit/2Cell (X4.5) NAND Flash Memory: Half Bit technology. - Noboru Shibata; Hironori Uchikawa; Taira Shibuya; Kenri Nakai; Kosuke Yanagidaira; Hirofumi Inoue (IMW, 2023)

Joint BCH and XOR Decoding for Solid State Drives. - Naoko Kifune; Hironori Uchikawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory. - Noboru Shibata; Hironori Uchikawa; Taira Shibuya; Hirofumi Inoue (IMW, 2024)

A Relay Algorithm of BCH Codes for a Quick Start of the Berlekamp-Massey Algorithm. - Naoaki Kokubun; Yuki Kondo; Hironori Uchikawa (ISIT, 2024)

Fast Readable Multi-Cell Coding for Flash Memory. - Hironori Uchikawa; Noboru Shibata; Taira Shibuya (ISIT, 2024)

Double-Stack Erasure-Filled Channel and Level-By-Level Error Correction. - Hironori Uchikawa; Manabu Hagiwara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)