An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM. - Hironori Yamauchi; Takao Kaneko; Tsutomu Kobayashi; Atsushi Iwata; Sadayasu Ono (ICASSP, 1985)

A 50ns floating-point signal processor VLSI. - Takao Kaneko; Hironori Yamauchi; Atsushi Iwata (ICASSP, 1986)

A real-time 256×256 point two-dimensional FFT single-chip processor. - Hiroshi Miyanaga; Hironori Yamauchi; Kazuhiro Matsuda (ICASSP, 1991)

A highly-parallel single-chip DSP architecture for video signal processing. - Hironori Yamauchi; Yutaka Tashiro; Toshihiro Minami; Yutaka Suzuki (ICASSP, 1991)

An Organized Firmware Verification Environment for the Programmable Image DSP. - Yutaka Tashiro; Hironori Yamauchi; Toshihiro Minami; Tetsuo Tajiri; Yutaka Suzuki (ITC, 1991)

A 300-MPOS video signal processor with a parallel architecture. - Toshihiro Minami; Ryota Kasai; Hironori Yamauchi; Yutaka Tashiro; Jun-ichi Takahashi; Shigeru Date (IEEE J. Solid State Circuits, 1991)

Architecture and implementation of a highly parallel single-chip video DSP. - Hironori Yamauchi; Yutaka Tashiro; Toshihiro Minami; Yutaka Suzuki (IEEE Trans. Circuits Syst. Video Technol., 1992)

Guest Editors' Introduction. - Keshab K. Parhi; Takao Nishitani; Hironori Yamauchi (J. VLSI Signal Process., 1997)

Scalable GA processor architecture and its implementation of processor-element. - Tetsuya Imai; Masaya Yoshikawa; Hidekazu Terai; Hironori Yamauchi (ICASSP, 2002)

Blurred Image Restoration by Using Real-Coded Genetic Algorithm. - Hideto Nishikado; Hiroyuki Murata; Motonori Yamaji; Hironori Yamauchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

VLSI processor architecture for real-time GA processing and PE-VLSI design. - Tetsuya Imai; Masaya Yoshikawa; Hidekazu Terai; Hironori Yamauchi (ISCAS (3), 2004)

Video watermarking for digital cinema contents. - Sadi Vural; Hiromi Tomii; Hironori Yamauchi (EUSIPCO, 2005)

Traceable robust watermarking for digital cinema system. - Sadi Vural; Hiromi Tomii; Hironori Yamauchi (ISSPA, 2005)

DWT Based Robust Watermarking Embed Using CRC-32 Techniques. - Sadi Vural; Hiromi Tomii; Hironori Yamauchi (WEC (5), 2005)

Configurable multi-processor architecture and its processor element design. - Tsutomu Nishimura; Takuji Miki; Hiroaki Sugiura 003; Yuki Matsumoto; Masatsugu Kobayashi; Toshiyuki Kato; Tsutomu Eda; Hironori Yamauchi (ASP-DAC, 2006)

Human Behavior Recognition for Daily Task Assistance using Sparse Range Data Observations. - Akira Utsumi; Hirotake Yamazoe; Shinji Abe; Daisuke Kanbara; Hironori Yamauchi (ICARCV, 2006)

A CDFG generating method from C program for LSI design. - Toshiyuki Kato; Takaaki Miyauchi; Yoshizo Osumi; Hironori Yamauchi; Hideto Nishikado; Takaaki Miyake; Shiro Kobayashi (APCCAS, 2008)

Hybrid Architecture of Genetic Algorithm and Simulated Annealing. - Masaya Yoshikawa; Hironori Yamauchi; Hidekazu Terai (Eng. Lett., 2008)

A Gabor Pseudo Fisherface Based Face Recognition Algorithm for LSI Implementation. - Yohei Fukumizu; Tomoaki Takano; Yasuyuki Oshima; Toshihiko Terada; Hironori Yamauchi (IIH-MSP, 2009)

Signal and noise separation in medical diagnostic system based on independent component analysis. - Abdullah K. Khan; Tatsuya Onoue; Kenji Hashiodani; Yohei Fukumizu; Hironori Yamauchi (APCCAS, 2010)

Robustly separating sound components in human body based on 2-ch ICA and EM algorithm with dirichlet distribution. - Kenji Hashiodani; S. Takada; Yohei Fukumizu; Hironori Yamauchi; Yoshimasa Kurumi; Tohru Tani (BHI, 2012)

Improved face image super-resolution with restricted patch-searching area. - Suhail Hamdan; Yohei Fukumizu; Tomonori Izumi; Hironori Yamauchi (ICCSP, 2019)