An Architecture for WSI Rapid Prototyping. - Vijay K. Jain; Hiroomi Hikawa; David C. Keezer (Computer, 1992)

A radix-8 wafer scale FFT processor. - Earl E. Swartzlander Jr.; Vijay K. Jain; Hiroomi Hikawa (J. VLSI Signal Process., 1992)

Parallel Architecture for Universal Digital Signal Processing. - Vijay K. Jain; Hiroomi Hikawa (HICSS (1), 1994)

Implementation of simplified multilayer neural networks with on-chip learning. - Hiroomi Hikawa (ICNN, 1995)

An efficient pulse mode multilayer neural network. - Hiroomi Hikawa (ISCAS (5), 1999)

Implementation of multilayer neural network with threshold neurons and its analysis. - Kazuo Sato; Hiroomi Hikawa (Artif. Life Robotics, 1999)

Frequency-based multilayer neural network with on-chip learning and enhanced neuron characteristics. - Hiroomi Hikawa (IEEE Trans. Neural Networks, 1999)

Pulse Mode Multilayer Neural Network with Floating Point Operation and On-Chip Learning. - Hiroomi Hikawa (IJCNN (2), 2000)

Pulse mode multilayer neural network based on floating point number representation. - Hiroomi Hikawa (ISCAS, 2000)

An efficient three-valued multilayer neural network with on-chip learning suitable for hardware implementation. - Hiroomi Hikawa (Syst. Comput. Jpn., 2000)

Digital pulse mode neural network with simple synapse multiplier. - Hiroomi Hikawa (ISCAS (3), 2001)

Pulse mode neuron with leakage integrator and additive random noise. - Hiroomi Hikawa (ISCAS (5), 2003)

A multilayer neural network with pulse position modulation. - Hiroomi Hikawa (Syst. Comput. Jpn., 2003)

A new digital pulse-mode neuron with adjustable activation function. - Hiroomi Hikawa (IEEE Trans. Neural Networks, 2003)

A digital hardware pulse-mode neuron with piecewise linear activation function. - Hiroomi Hikawa (IEEE Trans. Neural Networks, 2003)

Digital pulse mode neuron with robust nonlinear activation function. - Hiroomi Hikawa (IJCNN, 2004)

Direct digital frequency synthesizer with multi-stage linear interpolation. - Hiroomi Hikawa (ISCAS (4), 2004)

A new pulse mode self organizing map hardware with digital phase locked loops. - Hiroomi Hikawa (IJCNN, 2005)

Hardware friendly vector quantization algorithm. - Shigeki Matsubara; Hiroomi Hikawa (ISCAS (4), 2005)

FPGA implementation of self organizing map with digital phase locked loops. - Hiroomi Hikawa (Neural Networks, 2005)

Vector Quantization System Based on Scalar SOM/AND-OR Hybrid Network. - Hiroomi Hikawa (IJCNN, 2006)

Japanese Hand Sign Recognition System. - Hirotada Fujimura; Yuuichi Sakai; Hiroomi Hikawa (ICONIP (1), 2007)

A New Hardware Friendly Vector Distance Evaluation Function for Vector Classifiers. - Hiroomi Hikawa; Kaori Kugimiya (ICONIP (2), 2007)

Pseudo RBF Network for Position Independent Hand Posture Recognition System. - Hiroomi Hikawa; Shigeki Matsubara (IJCNN, 2007)

Performance Comparison of SOM Based Hybrid Hardware Classifiers. - Hiroomi Hikawa; Taku Miyanishi; Kousuke Tamaya (IJCNN, 2007)

Hardware Feedback Self-Organizing Map and its Application to Mobile Robot Location Identification. - Hiroomi Hikawa; Kazutoshi Harada; Takenori Hirabayashi (J. Adv. Comput. Intell. Intell. Informatics, 2007)

Hardware Design of Japanese Hand Sign Recognition System. - Hiroomi Hikawa; Hirotada Fujimura (ICONIP (2), 2008)

On simultaneous perturbation particle swarm optimization. - Yutaka Maeda; Naoto Matsushita; Seiji Miyoshi; Hiroomi Hikawa (IEEE Congress on Evolutionary Computation, 2009)

On automatic generation of VHDL code for self-organizing map. - Akira Onoo; Hiroomi Hikawa; Seiji Miyoshi; Yutaka Maeda (IJCNN, 2009)

Hand sign recognition system based on hybrid network classifier. - Yuuki Taki; Hiroomi Hikawa; Seiji Miyoshi; Yutaka Maeda (IJCNN, 2009)

DDFS with New Sinusoid Approximation based on Harmonics Removal. - Hiroomi Hikawa (ISCAS, 2009)

Statistical Mechanical Analysis of Simultaneous Perturbation Learning. - Seiji Miyoshi; Hiroomi Hikawa; Yutaka Maeda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Image compression with hardware self-organizing map. - Hiroomi Hikawa; Kenji Doumoto; Simone Miyoshi; Yutaka Maeda (IJCNN, 2010)

Comparison of range check classifier and hybrid network classifier for hand sign recognition system. - Hiroomi Hikawa; Seito Yamazaki; Tatsuya Ando; Simone Miyoshi; Yutaka Maeda (IJCNN, 2010)

Phase amplitude converter with conditional shift operation. - Hiroomi Hikawa; Taketo Namba (ISCAS, 2010)

Learning Scheme for Complex Neural Networks Using Simultaneous Perturbation. - Yutaka Maeda; Takahiro Yamada; Seiji Miyoshi; Hiroomi Hikawa (ICANN (2), 2011)

Study on gesture recognition system using posture classifier and Jordan recurrent neural network. - Hiroomi Hikawa; Yusuke Araga (IJCNN, 2011)

Hardware design of a color quantization with self-organizing map. - Yoshiro Oba; Kota Yamamoto; Takahiro Nagai; Hiroomi Hikawa (ISPACS, 2011)

Automatic generation of hardware self-organizing map for FPGA implementation. - Kota Yamamoto; Yoshiro Oba; Zuiko Rikuhashi; Hiroomi Hikawa (ISPACS, 2011)

Hand sign recognition system based on SOM-Hebb hybrid network. - Hiroomi Hikawa; Keishi Kaida (SMC, 2011)

ROM-Less Phase to Amplitude Converter Using Sine Wave Approximation Based on Harmonic Removal from Trapezoid Wave. - Hiroomi Hikawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Real time gesture recognition system using posture classifier and Jordan recurrent neural network. - Yusuke Araga; Makoto Shirabayashi; Keishi Kaida; Hiroomi Hikawa (IJCNN, 2012)

Sequential vector classifier based on SOM and feedback Hebbian network. - Yusuke Araga; Zuiko Rikuhashi; Hiroomi Hikawa (ISPACS, 2012)

DPLL based hardware SOM with a new winner-take-all circuit. - Hiroomi Hikawa (IJCNN, 2013)

A new winner-take-all neural network using DPLL and phase modulated signal. - Masaki Azuma; Hiroomi Hikawa (ISPACS, 2013)

Color-space image compression with hardware Self-organizing map. - Naoki Terahara; Yoshiro Oba; Hiroomi Hikawa (ISPACS, 2013)

Supervised learning of DPLL based winner-take-all neural network. - Masaki Azuma; Hiroomi Hikawa (ICES, 2014)

Low-power wiring method in CMOS logics circuits by segmentation coding and pseudo majority voting. - Katsuhiko Ueda; Zuiko Rikuhashi; Kentaro Hayashi; Hiroomi Hikawa (ISCAS, 2014)

Vector classification by a winner-take-all neural network with digital frequency-locked loop. - Hiroomi Hikawa (IJCNN, 2015)

Winner-take-all neural network with digital frequency-locked loop. - Hiroomi Hikawa (ISCAS, 2015)

Scalable Hardware Winner-Take-All Neural Network with DPLL. - Masaki Azuma; Hiroomi Hikawa (IEICE Trans. Inf. Syst., 2015)

Low-Power Wiring Method for Band-Limited Signals in CMOS Logic Circuits by Segmentation Coding with Pseudo-Majority Voting. - Katsuhiko Ueda; Zuiko Rikuhashi; Kentaro Hayashi; Hiroomi Hikawa (IEICE Trans. Electron., 2015)

Novel FPGA Implementation of Hand Sign Recognition System With SOM-Hebb Classifier. - Hiroomi Hikawa; Keishi Kaida (IEEE Trans. Circuits Syst. Video Technol., 2015)

Improved Learning Performance of Hardware Self-Organizing Map Using a Novel Neighborhood Function. - Hiroomi Hikawa; Yutaka Maeda (IEEE Trans. Neural Networks Learn. Syst., 2015)

Improved winner-take-all circuit for neural network based on frequency-modulated signals. - Hiroomi Hikawa (ICECS, 2016)

Gesture Spotting by Using Vector Distance of Self-organizing Map. - Yuta Ichikawa; Shuji Tashiro; Hidetaka Ito; Hiroomi Hikawa (ICONIP (2), 2016)

Live demonstration: Off-chip learning for hardware hand-sign recognition system. - Masayuki Tamaki; Hiroomi Hikawa (ISCAS, 2016)

Off-chip learning for hardware hand-sign recognition system. - Masayuki Tamaki; Hiroomi Hikawa (ISCAS, 2016)

Real time gesture recognition system with gesture spotting function. - Yuta Ichikawa; Shuji Tashiro; Hidetaka Ito; Hiroomi Hikawa (SSCI, 2016)

Effect of grouping in vector recognition system based on SOM. - Masayoshi Ohta; Yuto Kurosaki; Hidetaka Ito; Hiroomi Hikawa (SSCI, 2016)

A New Hardware Self-Organizing Map Architecture with High Expandability. - Hiroomi Hikawa; Hidetaka Ito; Yutaka Maeda (IPAS, 2018)

Hardware Self-Organizing Map Based on Frequency-Modulated Signal and Digital Frequency-Locked Loop. - Hiroomi Hikawa; Hidetaka Ito; Yutaka Maeda (ISCAS, 2018)

A New Self-Organizing Map with Continuous Learning Capability. - Hiroomi Hikawa; Hidetaka Ito; Yutaka Maeda (SSCI, 2018)

Off-Chip Training with Additive Perturbation for FPGA-Based Hand Sign Recognition System. - Hiroomi Hikawa; Masayuki Tamaki; Hidetaka Ito (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

A Subspace Newton-Type Method for Approximating Transversely Repelling Chaotic Saddles. - Hidetaka Ito; Hiroomi Hikawa; Yutaka Maeda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

SOM-Based Vector Recognition with Pre-Grouping Functionality. - Yuto Kurosaki; Masayoshi Ohta; Hidetaka Ito; Hiroomi Hikawa (IEICE Trans. Inf. Syst., 2018)

Nested Hardware Architecture for Self-Organizing Map. - Hiroomi Hikawa (IJCNN, 2019)

Nested Pipeline Hardware Self-Organizing Map for High Dimensional Vectors. - Hiroomi Hikawa (ICECS, 2020)

A Synthesis Method of Spiking Neural Oscillators with Considering Asymptotic Stability. - Yasuaki Kuroe; Seiji Miyoshi; Hiroomi Hikawa; Hidetaka Ito; Kimiko Motonaka; Yutaka Maeda (IJCNN, 2021)

Hardware Self-Organizing Map Based on Digital Frequency-Locked Loop and Triangular Neighborhood Function. - Hiroomi Hikawa (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Survey of Hardware Self-Organizing Maps. - Slavisa Jovanovic; Hiroomi Hikawa (IEEE Trans. Neural Networks Learn. Syst., 2023)

Electroencephalogram-Based Facial Gesture Recognition Using Self-Organizing Map. - Takahiro Kawaguchi; Koki Ono; Hiroomi Hikawa (Sensors, 2024)

Hardware Self-Organizing Map With Dithered Step Neighborhood Function. - Hiroomi Hikawa (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)