Experimental study on body-biasing layout style– negligible area overhead enables sufficient speed controllability –. - Koichi Hamamoto; Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (ACM Great Lakes Symposium on VLSI, 2008)

Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. - Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (ISLPED, 2008)

Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. - Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (CICC, 2009)

Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. - Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. - Koichi Hamamoto; Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (IEICE Trans. Electron., 2009)

Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. - Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (ASP-DAC, 2010)

Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. - Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates. - Hiroshi Fuketa; Satoshi Iida; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (DAC, 2011)

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics. - Hiroshi Fuketa; Koji Hirairi; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (ISLPED, 2011)

Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. - Tadashi Yasufuku; Satoshi Iida; Hiroshi Fuketa; Koji Hirairi; Masahiro Nomura; Makoto Takamiya; Takayasu Sakurai (ISLPED, 2011)

An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion. - Hiroshi Fuketa; Dan Kuroda; Masanori Hashimoto; Takao Onoye (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. - Hiroshi Fuketa; Ryo Takahashi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (CICC, 2012)

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits. - Tadashi Yasufuku; Koji Hirairi; Yu Pu; Yun Fei Zheng; Ryo Takahashi; Masato Sasaki; Hiroshi Fuketa; Atsushi Muramatsu; Masahiro Nomura; Hirofumi Shinohara; Makoto Takamiya; Takayasu Sakurai (ISQED, 2012)

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. - Koji Hirairi; Yasuyuki Okuma; Hiroshi Fuketa; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (ISSCC, 2012)

Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits. - Koichi Ishida; Tsung-Ching Huang; Kentaro Honda; Yasuhiro Shinozuka; Hiroshi Fuketa; Tomoyuki Yokota; Ute Zschieschang; Hagen Klauk; Gregory Tortissier; Tsuyoshi Sekitani; Makoto Takamiya; Hiroshi Toshiyoshi; et al. (ISSCC, 2012)

Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. - Ryo Takahashi; Hidehiro Takata; Tadashi Yasufuku; Hiroshi Fuketa; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. - Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (IEEE Trans. Very Large Scale Integr. Syst., 2012)

On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS. - Xin Zhang 025; Koichi Ishida; Hiroshi Fuketa; Makoto Takamiya; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Variation-aware subthreshold logic circuit design. - Hiroshi Fuketa; Ryo Takahashi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (ASICON, 2013)

Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme. - Yasuhiro Shinozuka; Hiroshi Fuketa; Koichi Ishida; Futoshi Furuta; Kenichi Osada; Kenichi Takeda; Makoto Takamiya; Takayasu Sakurai (ISQED, 2013)

Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits. - Hiroshi Fuketa; Masahiro Nomura; Makoto Takamiya; Takayasu Sakurai (ISSCC, 2013)

1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control. - Hiroshi Fuketa; Kazuaki Yoshioka; Yasuhiro Shinozuka; Koichi Ishida; Tomoyuki Yokota; Naoji Matsuhisa; Yusuke Inoue 002; Masaki Sekino; Tsuyoshi Sekitani; Makoto Takamiya; Takao Someya; Takayasu Sakurai (ISSCC, 2013)

Large-area and flexible sensors with organic transistors. - Hiroshi Fuketa; Koichi Ishida; Tsuyoshi Sekitani; Makoto Takamiya; Takao Someya; Takayasu Sakurai (IWASI, 2013)

Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. - Hiroshi Fuketa; Ryo Takahashi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE J. Solid State Circuits, 2013)

Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits. - Koichi Ishida; Tsung-Ching Huang; Kentaro Honda; Yasuhiro Shinozuka; Hiroshi Fuketa; Tomoyuki Yokota; Ute Zschieschang; Hagen Klauk; Gregory Tortissier; Tsuyoshi Sekitani; Hiroshi Toshiyoshi; Makoto Takamiya; et al. (IEEE J. Solid State Circuits, 2013)

Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique. - Hiroshi Fuketa; Koji Hirairi; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2013)

An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting. - Hiroshi Fuketa; Youichi Momiyama; Atsushi Okamoto; Tsuyoshi Sakata; Makoto Takamiya; Takayasu Sakurai (ESSCIRC, 2014)

30.3 Organic-transistor-based 2kV ESD-tolerant flexible wet sensor sheet for biomedical applications with wireless power and data transmission using 13.56MHz magnetic resonance. - Hiroshi Fuketa; Kazuaki Yoshioka; Tomoyuki Yokota; Wakako Yukita; Mari Koizumi; Masaki Sekino; Tsuyoshi Sekitani; Makoto Takamiya; Takao Someya; Takayasu Sakurai (ISSCC, 2014)

Flexible, large-area, and distributed organic electronics closely contacted with skin for healthcare applications. - Makoto Takamiya; Hiroshi Fuketa; Koichi Ishida; Tomoyuki Yokota; Tsuyoshi Sekitani; Takao Someya; Takayasu Sakurai (MWSCAS, 2014)

92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator. - Shunta Iguchi; Hiroshi Fuketa; Takayasu Sakurai; Makoto Takamiya (VLSIC, 2014)

Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. - Hiroshi Fuketa; Masahiro Nomura; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2014)

1 µm-Thickness Ultra-Flexible and High Electrode-Density Surface Electromyogram Measurement Sheet With 2 V Organic Transistors for Prosthetic Hand Control. - Hiroshi Fuketa; Kazuaki Yoshioka; Yasuhiro Shinozuka; Koichi Ishida; Tomoyuki Yokota; Naoji Matsuhisa; Yusuke Inoue 002; Masaki Sekino; Tsuyoshi Sekitani; Makoto Takamiya; Takao Someya; Takayasu Sakurai (IEEE Trans. Biomed. Circuits Syst., 2014)

Analysis to optimize sensitivity of RF energy harvester with voltage boost circuit. - Dan Luo; Hiroshi Fuketa; Kenichi Matsunaga; Hiroki Morimura; Makoto Takamiya; Takayasu Sakurai (ECCTD, 2015)

248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting. - Teruki Someya; Hiroshi Fuketa; Kenichi Matsunaga; Hiroki Morimura; Takayasu Sakurai; Makoto Takamiya (ESSCIRC, 2015)

Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applications. - Yoshitaka Yamauchi; Yuki Yanagihara; Hiroshi Fuketa; Takayasu Sakurai; Makoto Takamiya (ICICDT, 2015)

16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits. - Hiroshi Fuketa; Masamune Hamamatsu; Tomoyuki Yokota; Wakako Yukita; Teruki Someya; Tsuyoshi Sekitani; Makoto Takamiya; Takao Someya; Takayasu Sakurai (ISSCC, 2015)

Wireless Power Transfer With Zero-Phase-Difference Capacitance Control. - Shunta Iguchi; Pyungwoo Yeon; Hiroshi Fuketa; Koichi Ishida; Takayasu Sakurai; Makoto Takamiya (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster. - Shunta Iguchi; Hiroshi Fuketa; Takayasu Sakurai; Makoto Takamiya (IEEE J. Solid State Circuits, 2016)

Session 15 overview: Innovations in technologies and circuits. - Jan Genoe; Hiroshi Fuketa; Eugenio Cantatore (ISSCC, 2017)

Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier. - Teruki Someya; Hiroshi Fuketa; Kenichi Matsunaga; Hiroki Morimura; Takayasu Sakurai; Makoto Takamiya (IEICE Trans. Electron., 2017)

Fully Integrated, 100-mV Minimum Input Voltage Converter With Gate-Boosted Charge Pump Kick-Started by LC Oscillator for Energy Harvesting. - Hiroshi Fuketa; Shin-ichi O'Uchi; Takashi Matsukawa (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 0.3-V 1-µW Super-Regenerative Ultrasound Wake-Up Receiver With Power Scalability. - Hiroshi Fuketa; Shin-ichi O'Uchi; Takashi Matsukawa (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop. - Hiroshi Fuketa; Shin-ichi O'Uchi; Takashi Matsukawa (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Image-Classifier Deep Convolutional Neural Network Training by 9-bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format. - Shin-ichi O'Uchi; Hiroshi Fuketa; Tsutomu Ikegami; Wakana Nogami; Takashi Matsukawa; Tomohiro Kudoh; Ryousei Takano (ISCAS, 2018)

Ultra-low Power Human Motion Detection Sensor using Electrostatic Induction and Demonstration of Contactless Remote Light Switch. - Hiroshi Fuketa; Yukinori Morita (GCCE, 2019)

Neural ODE with Temporal Convolution and Time Delay Neural Networks for Small-Footprint Keyword Spotting. - Hiroshi Fuketa; Yukinori Morita (CoRR, 2020)

Edge Artificial Intelligence Chips for the Cyberphysical Systems Era. - Hiroshi Fuketa; Kunio Uchiyama (Computer, 2021)

Ultra-Low Power Hand Gesture Sensor Using Electrostatic Induction. - Hiroshi Fuketa (Sensors, 2021)

A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution. - Hiroshi Fuketa; Ippei Akita; Tomohiro Ishikawa; Hanpei Koike; Takahiro Mori (VLSI Technology and Circuits, 2022)

Time-Delay-Neural-Network-Based Audio Feature Extractor for Ultra-Low Power Keyword Spotting. - Hiroshi Fuketa (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Determining the low-frequency noise source in cryogenic operation of short-channel bulk MOSFETs. - Takumi Inaba; Hiroshi Oka; Hidehiro Asai; Hiroshi Fuketa; Shota Iizuka; Kimihiko Kato; Shunsuke Shitakata; Koichi Fukuda; Takahiro Mori (VLSI Technology and Circuits, 2023)

Origin of Low-Frequency Noise in Si n-MOSFET at Cryogenic Temperatures: The Effect of Interface Quality. - Hiroshi Oka; Takumi Inaba; Shunsuke Shitakata; Kimihiko Kato; Shota Iizuka; Hidehiro Asai; Hiroshi Fuketa; Takahiro Mori (IEEE Access, 2023)

Lookup Table-Based Computing-in-Memory Macro Approximating Dot Products Without Multiplications for Energy-Efficient CNN Inference. - Hiroshi Fuketa (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout. - Hiroshi Fuketa; Ippei Akita; Tomohiro Ishikawa; Hanpei Koike; Takahiro Mori (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation. - Hiroshi Fuketa; Toshihiro Katashita; Yohei Hori; Masakazu Hioki (IEEE Access, 2024)

Temperature Dependent Variations of Low-Frequency Noise Sources in Cryogenic Short-Channel Bulk MOSFETs. - Takumi Inaba; Hiroshi Oka; Hidehiro Asai; Hiroshi Fuketa; Shota Iizuka; Kimihiko Kato; Shunsuke Shitakata; Koichi Fukuda; Takahiro Mori (IEEE Access, 2024)

Fully Quantized Matrix Arithmetic-Only BERT Model and Its FPGA-Based Accelerator. - Hiroshi Fuketa; Toshihiro Katashita; Yohei Hori; Masakazu Hioki (IEEE Access, 2025)