Throughput-Optimal Hardware Implementation of LZW Decompression on the FPGA. - Hiroshi Kagawa; Yasuaki Ito; Koji Nakano (CANDAR Workshops, 2019)

Fully-Pipelined Architecture for Simulated Annealing-based QUBO Solver on the FPGA. - Hiroshi Kagawa; Yasuaki Ito; Koji Nakano; Ryota Yasudo; Yuya Kawamata; Ryota Katsuki; Yusuke Tabata; Takashi Yazane; Kenichiro Hamano (CANDAR, 2020)

High-throughput FPGA implementation for quadratic unconstrained binary optimization. - Hiroshi Kagawa; Yasuaki Ito; Koji Nakano; Ryota Yasudo; Yuya Kawamata; Ryota Katsuki; Yusuke Tabata; Takashi Yazane; Kenichiro Hamano (Concurr. Comput. Pract. Exp., 2023)