An Automatic Translation System Of Non-Segmented Kana Sentences Into Kanji-Kana Sentences. - Hiroshi Makino; Makoto Kizawa (COLING, 1980)

Beta: An Automatic Kana-Kanji Translation System. - Hiroshi Makino (Computer, 1985)

Development of the Spherical SCARA Robot. - Hiroshi Makino (J. Robotics Mechatronics, 1989)

A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature. - Hiroshi Makino; Shuichi Matsue; Minoru Noda; Noriyuki Tanino; Satoshi Takano; Kazuo Nishitani; Shimpei Kayano (IEEE J. Solid State Circuits, 1990)

A 5-ns GaAs 16-kb SRAM. - Shuichi Matsue; Hiroshi Makino; Minoru Noda; Hirofumi Nakano; Satoshi Takano; Kazuo Nishitani; Shimpei Kayano (IEEE J. Solid State Circuits, 1991)

A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. - Hiroshi Makino; Yasunobu Nakase; Hirofumi Shinohara (ICCD, 1993)

A BiCMOS wired-OR logic. - Yasunobu Nakase; Hiroaki Suzuki; Hiroshi Makino; Hirofumi Shinohara; Koichiro Mashiko (IEEE J. Solid State Circuits, 1995)

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. - Hiroshi Makino; Yasunobu Nakase; Hiroaki Suzuki; Hiroyuki Morinaka; Hirofumi Shinohara; Koichiro Mashiko (IEEE J. Solid State Circuits, 1996)

A 286 MHz 64-b floating point multiplier with enhanced CG operation. - Hiroshi Makino; Hiroaki Suzuki; Hiroyuki Morinaka; Yasunobu Nakase; Koichiro Mashiko; Tadashi Sumi (IEEE J. Solid State Circuits, 1996)

Leading-zero anticipatory logic for high-speed floating point addition. - Hiroaki Suzuki; Hiroyuki Morinaka; Hiroshi Makino; Yasunobu Nakase; Koichiro Mashiko; Tadashi Sumi (IEEE J. Solid State Circuits, 1996)

A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme. - Hiroaki Suzuki; Hiroshi Makino; Koichiro Mashiko; Hisanori Hamano (ICCD, 1997)

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. - Vojin G. Oklobdzija; Hiroaki Suzuki; Hiroyuki Morinaka; Hiroshi Makino; Yasunobu Nakase; Koichiro Mashiko; Tadashi Sumi (IEEE J. Solid State Circuits, 1997)

Authors Reply. - Hiroaki Suzuki; Hiroyuki Morinaka; Hiroshi Makino; Yasunobu Nakase; Koichiro Mashiko (IEEE J. Solid State Circuits, 1997)

A low power SRAM using auto-backgate-controlled MT-CMOS. - Koji Nii; Hiroshi Makino; Yoshiki Tsujihashi; Chikayoshi Morishima; Yasushi Hayakawa; Hiroyuki Nunogami; Takahiko Arakawa; Hisanori Hamano (ISLPED, 1998)

Robot contest "Robocon Yamanashi". - Noriaki Kiyohiro; Hiroshi Makino; Hideo Mori (J. Robotics Mechatronics, 1998)

A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. - Niichi Itoh; Yuka Naemura; Hiroshi Makino; Yasunobu Nakase; Tsutomu Yoshihara; Yasutaka Horiba (IEEE J. Solid State Circuits, 2001)

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. - Koji Nii; Yasumasa Tsukamoto; Tomoaki Yoshizawa; Susumu Imaoka; Yoshinobu Yamagami; Toshikazu Suzuki; Akinori Shibayama; Hiroshi Makino; Shuhei Iwade (IEEE J. Solid State Circuits, 2004)

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. - Yasumasa Tsukamoto; Koji Nii; Susumu Imaoka; Yuji Oda; Shigeki Ohbayashi; Tomoaki Yoshizawa; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara (ICCAD, 2005)

A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. - Niichi Itoh; Yasumasa Tsukamoto; Takeshi Shibagaki; Koji Nii; Hidehiro Takata; Hiroshi Makino (ISCAS (1), 2005)

Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs. - Mitsuya Fukazawa; Tetsuro Matsuno; Toshifumi Uemura; Rei Akiyama; Tetsuya Kagemoto; Hiroshi Makino; Hidehiro Takata; Makoto Nagata (ISSCC, 2007)

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. - Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; et al. (ISSCC, 2007)

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. - Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (ISSCC, 2007)

Research and Commercialization of SCARA Robot -The Case of Industry-University Joint Research and Development-. - Hiroshi Makino; Akitaka Kato; Yasunori Yamazaki (Int. J. Autom. Technol., 2007)

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. - Shigeki Ohbayashi; Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Susumu Imaoka; Yuji Oda; Tsutomu Yoshihara; Motoshige Igarashi; Masahiko Takeuchi; Hiroshi Kawashima; Yasuo Yamaguchi; Kazuhiro Tsukamoto; et al. (IEEE J. Solid State Circuits, 2007)

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. - Masako Fujii; Hiroaki Suzuki; Hiromi Notani; Hiroshi Makino; Hirofumi Shinohara (ESSCIRC, 2008)

Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. - Hiroaki Suzuki; Masanori Kurimoto; Tadao Yamanaka; Hidehiro Takata; Hiroshi Makino; Hirofumi Shinohara (ISLPED, 2008)

A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology. - Masako Fujii; Koji Nii; Hiroshi Makino; Shigeki Ohbayashi; Motoshige Igarashi; Takeshi Kawamura; Miho Yokota; Nobuhiro Tsuda; Tomoaki Yoshizawa; Toshikazu Tsutsui; Naohiko Takeshita; Naofumi Murata; et al. (IEICE Trans. Electron., 2008)

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. - Satoshi Ishikura; Marefusa Kurumada; Toshio Terano; Yoshinobu Yamagami; Naoki Kotani; Katsuji Satomi; Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Toshiyuki Oashi; Hiroshi Makino; et al. (IEEE J. Solid State Circuits, 2008)

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. - Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (IEEE J. Solid State Circuits, 2008)

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. - Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; et al. (IEEE J. Solid State Circuits, 2008)

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. - Koji Nii; Yasumasa Tsukamoto; Makoto Yabuuchi; Yasuhiro Masuda; Susumu Imaoka; Keiichi Usui; Shigeki Ohbayashi; Hiroshi Makino; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2009)

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. - Shunji Nakata; Hirotsugu Suzuki; Ryota Honda; Takahito Kusumoto; Shin'ichiro Mutoh; Hiroshi Makino; Masayuki Miyama; Yoshio Matsuda (ISCAS, 2010)

Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation. - Shunji Nakata; Shin'ichiro Mutoh; Hiroshi Makino; Masayuki Miyama; Yoshio Matsuda (IEICE Electron. Express, 2010)

Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. - Hiroshi Makino; Shunji Nakata; Hirotsugu Suzuki; Shin'ichiro Mutoh; Masayuki Miyama; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current. - Shunji Nakata; Ryota Honda; Hiroshi Makino; Hiroki Morimura; Yoshio Matsuda (MWSCAS, 2012)

Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. - Hiroshi Makino; Shunji Nakata; Hirotsugu Suzuki; Shin'ichiro Mutoh; Masayuki Miyama; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IET Circuits Devices Syst., 2012)

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology. - Shunji Nakata; Ryota Honda; Hiroshi Makino; Shin'ichiro Mutoh; Masayuki Miyama; Yoshio Matsuda (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop. - Tsutomu Yoshimura; Shuhei Iwade; Hiroshi Makino; Yoshio Matsuda (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

The LSI implementation of a memory based field programmable device for MCU peripherals. - Tetsuya Matsumura; Naoya Okada; Yoshifumi Kawamura; Koji Nii; Kazutami Arimoto; Hiroshi Makino; Yoshio Matsuda (DDECS, 2014)

A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance. - Shunji Nakata; Hiroshi Makino; Yoshio Matsuda (MWSCAS, 2014)

Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current. - Shunji Nakata; Hiroshi Makino; Ryota Honda; Masayuki Miyama; Yoshio Matsuda (J. Circuits Syst. Comput., 2014)

Development of the SCARA. - Hiroshi Makino (J. Robotics Mechatronics, 2014)

Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. - Shunji Nakata; Hiroshi Makino; Junpei Hosokawa; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. - Shunji Nakata; Hiroki Hanazono; Hiroshi Makino; Hiroki Morimura; Masayuki Miyama; Yoshio Matsuda (IEEE Trans. Very Large Scale Integr. Syst., 2014)

The Challenge of Collaboration among Academies and Asia Pacific for ITS R&D. - Hiroshi Makino; Shunsuke Kamijo (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A study on motion estimation algorithm for moving pictures. - Ryota Bnadou; Masahiro Hiramori; Shuhei Iwade; Hiroshi Makino; Tutomu Yoshimura; Yoshio Matsuda (GCCE, 2016)

A study on fast motion estimation algorithm. - Masahiro Hiramori; Ryota Bandou; Shuhei Iwade; Hiroshi Makino; Tsutomu Yoshimura; Yoshio Matsuda (GCCE, 2016)

A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. - Yoshifumi Kawamura; Naoya Okada; Yoshio Matsuda; Tetsuya Matsumura; Hiroshi Makino; Kazutami Arimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)